This check was broken. r3 does not contain the silicon revision anymore, so we need to reload it.
Signed-off-by: David Jander david@protonic.nl --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index ee4150d..6bb398f 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -39,7 +39,9 @@ orr r0, r0, #(1 << 23) /* disable write allocate combine */ orr r0, r0, #(1 << 22) /* disable write allocate */
- cmp r3, #0x10 /* r3 contains the silicon rev */ + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */ orrls r0, r0, #(1 << 25)