
Hi Shinya,
Thanks for your support and your code patches. I'm waiting for a Lauterbach trace32 to debug deeply the code and understand better the behaviour. I'll send you my feedback next week.
Best regards,
luigi
On sab, 2008-02-16 at 18:06 +0900, Shinya Kuribayashi wrote:
Shinya Kuribayashi wrote:
Shinya Kuribayashi wrote:
I think that on my application the UNCACHED_SDRAM should map the address on KSEG1 (how it is now) but this simply doesn't work. Instead, using the PHYSADDR(a) macro... the kernel is able to start.
I suspect that there are issues on cache management. Can be?
IMHO it's not related to cache.
How do you set ERL and EXL bits? Please try to clear them at the STATUS register initialization like:
reset: <snip>
/* STATUS register */ mfc0 k0, CP0_STATUS
li k1, ~ST0_IE
li k1, ~(ST0_ERL | ST0_EXL | ST0_IE) and k0, k1 mtc0 k0, CP0_STATUS
ERL and EXL disable exceptions. Due to this spec, we are in danger of overlooking something critical. If this change brings in new exception(s), please fix the causes of them first. Hope this helps.
Err, sorry for confusing example. Here's the right one:
diff --git a/cpu/mips/start.S b/cpu/mips/start.S index c92b162..02797f7 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -211,14 +211,20 @@ reset: mtc0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHHI
- /* Inhibit deffered WATCH exception */
- mfc0 k0, CP0_CAUSE
- li k1, ~(1UL << 22) # CP0.Cause.WP = 0
- and k0, k0, k1
- mtc0 k0, CP0_CAUSE
- /* STATUS register */
#ifdef CONFIG_TB0229 li k0, ST0_CU0 #else mfc0 k0, CP0_STATUS #endif
- li k1, ~ST0_IE
- and k0, k1
ori k0, (ST0_ERL | ST0_EXL | ST0_IE)
xori k0, (ST0_ERL | ST0_EXL) mtc0 k0, CP0_STATUS
/* CAUSE register */
Again, it's highy recommended to make sure U-Boot works fine under interrupts enabled (CP0.Status.IE=1), before digging into UNCACHED_ SDRAM problem.
Shinya
Industrie Dial Face S.p.A. Luigi Mantellini R&D - Software Industrie Dial Face S.p.A. Via Canzo, 4 20068 Peschiera Borromeo (MI), Italy Tel.: +39 02 5167 2813 Fax: +39 02 5167 2459 E-mail: luigi.mantellini@idf-hit.com