Allwinner a64 needs to clear the SIDDP bit from PHYCTL register once the phy_init done.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- arch/arm/mach-sunxi/usb_phy.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 93340c7..b9542f8 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -45,6 +45,7 @@ /* A83T specific control bits for PHY0 */ #define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5) #define SUNXI_PHY_CTL_SIDDQ BIT(3) +#define SUNXI_PHY_CTL_SIDDP BIT(1)
/* A83T HSIC specific bits */ #define SUNXI_EHCI_HS_FORCE BIT(20) @@ -249,6 +250,12 @@ void sunxi_usb_phy_init(int index) SUNXI_PHY_CTL_SIDDQ); } #endif + +#ifdef CONFIG_MACH_SUN50I + if (phy->id == 0) + clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, + SUNXI_PHY_CTL_SIDDP); +#endif }
void sunxi_usb_phy_exit(int index)