Commit 1565d54a7671a1 ("imx:mx6sxsabresd board spl support") introduced the SPL support, but described the memory layout incorrectly.
mx6sxsabresd board has two MT41K256M16HA-125 DDR3 chips.
Each MT41K256M16HA-125 has 16-bit width, giving a total bus width of 32 bits and 1GiB of RAM space, so fix the memory representation accordingly.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 2ff960e..1a1beaf 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -523,10 +523,11 @@ const struct mx6_mmdc_calibration mx6_mmcd_calib = { .p0_mpwrdlctl = 0x34363638, };
+/* MT41K256M16HA-125 */ static struct mx6_ddr3_cfg mem_ddr = { .mem_speed = 1600, .density = 4, - .width = 32, + .width = 16, .banks = 8, .rowaddr = 15, .coladdr = 10, @@ -553,8 +554,8 @@ static void ccgr_init(void) static void spl_dram_init(void) { struct mx6_ddr_sysinfo sysinfo = { - .dsize = mem_ddr.width/32, - .cs_density = 24, + .dsize = 1, /* 32-bit width total */ + .cs_density = 32, /* Probe full 32GiB range */ .ncs = 1, .cs1_mirror = 0, .rtt_wr = 2, @@ -567,7 +568,7 @@ static void spl_dram_init(void) .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ };
- mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); }