diff -purN OLD/board/xsengine/flash.c NEW/board/xsengine/flash.c
--- OLD/board/xsengine/flash.c	2005-10-05 00:04:25.000000000 +0200
+++ NEW/board/xsengine/flash.c	2006-02-15 12:13:44.000000000 +0100
@@ -75,12 +75,26 @@ static void flash_get_offsets (ulong bas
 
 	if (info->flash_id == FLASH_UNKNOWN) return;
 
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+        if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ||
+            (info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL256N ||
+            (info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL512N) {
 		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->start[i] = base + (i * 0x40000);
 			info->protect[i] = 0;
 		}
 	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base;
+			/*
+			 * The first 8 sectors are 8 kB,
+			 * all the other ones  are 64 kB
+			 */
+			base += (i >= 0x7F)
+				?  2 * (8 << 10)
+				:  2 * (64 << 10);
+		}
+	}
 }
 
 /*-----------------------------------------------------------------------
@@ -101,10 +115,14 @@ void flash_print_info  (flash_info_t *in
 	}
 
 	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AMLV640U:	printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
-				break;
 	case FLASH_S29GL064M:	printf ("S29GL064M (64Mbit, top boot sector size)\n");
 				break;
+	case FLASH_S29GL128N:	printf ("S29GL128N (128Mbit, uniform sector size)\n");
+				break;
+	case FLASH_S29GL256N:	printf ("S29GL256N (256Mbit, uniform sector size)\n");
+				break;
+	case FLASH_S29GL512N:	printf ("S29GL512N (512Mbit, uniform sector size)\n");
+				break;
 	default:		printf ("Unknown Chip Type\n");
 				break;
 	}
@@ -130,9 +148,7 @@ void flash_print_info  (flash_info_t *in
  */
 static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 {
-	short i;
 	ulong value;
-	ulong base = (ulong)addr;
 
 	/* Write auto select command: read Manufacturer ID */
 	addr[0x0555] = 0x00AA00AA;
@@ -170,17 +186,6 @@ static ulong flash_get_size (vu_long *ad
 		debug ("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
 			addr[14], addr[15]);
 		switch(addr[14]) {
-		case AMD_ID_LV640U_2:
-			if (addr[15] != AMD_ID_LV640U_3) {
-				debug ("Chip: AMLV640U -> unknown\n");
-				info->flash_id = FLASH_UNKNOWN;
-			} else {
-				debug ("Chip: AMLV640U\n");
-				info->flash_id += FLASH_AMLV640U;
-				info->sector_count = 128;
-				info->size = 0x01000000;
-			}
-			break;				/* => 16 MB	*/
 		case AMD_ID_GL064MT_2:
 			if (addr[15] != AMD_ID_GL064MT_3) {
 				debug ("Chip: S29GL064M-R3 -> unknown\n");
@@ -188,10 +193,43 @@ static ulong flash_get_size (vu_long *ad
 			} else {
 				debug ("Chip: S29GL064M-R3\n");
 				info->flash_id += FLASH_S29GL064M;
-				info->sector_count = 128;
+				info->sector_count = 135;
 				info->size = 0x01000000;
 			}
 			break;				/* => 16 MB	*/
+		case AMD_ID_GL128N_2:
+			if (addr[15] != AMD_ID_GL128N_3) {
+				debug ("Chip: S29GL128N -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: S29GL128N\n");
+				info->flash_id += FLASH_S29GL128N;
+				info->sector_count = 128;
+				info->size = 0x02000000;
+			}
+			break;				/* => 32 MB */
+		case AMD_ID_GL256N_2:
+			if (addr[15] != AMD_ID_GL256N_3) {
+				debug ("Chip: S29GL256N -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: S29GL256N\n");
+				info->flash_id += FLASH_S29GL256N;
+				info->sector_count = 256;
+				info->size = 0x04000000;
+			}
+			break;				/* => 64 MB	*/
+		case AMD_ID_GL512N_2:
+			if (addr[15] != AMD_ID_GL512N_3) {
+				debug ("Chip: S29GL512N -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: S29GL512N\n");
+				info->flash_id += FLASH_S29GL512N;
+				info->sector_count = 512;
+				info->size = 0x08000000;
+			}
+			break;				/* => 128 MB	*/
 		default:
 			debug ("Chip: *** unknown ***\n");
 			info->flash_id = FLASH_UNKNOWN;
@@ -204,39 +242,12 @@ static ulong flash_get_size (vu_long *ad
 		return (0);			/* => no or unknown flash */
 	}
 
-	/* set up sector start address table */
-	switch (value) {
-	case AMD_ID_MIRROR:
-		switch (info->flash_id & FLASH_TYPEMASK) {
-		/* only known types here - no default */
-		case FLASH_AMLV128U:
-		case FLASH_AMLV640U:
-		case FLASH_AMLV320U:
-			for (i = 0; i < info->sector_count; i++) {
-				info->start[i] = base;
-				base += 0x20000;
-			}
-			break;
-		case FLASH_AMLV320B:
-			for (i = 0; i < info->sector_count; i++) {
-				info->start[i] = base;
-				/*
-				 * The first 8 sectors are 8 kB,
-				 * all the other ones  are 64 kB
-				 */
-				base += (i < 8)
-					?  2 * ( 8 << 10)
-					:  2 * (64 << 10);
-			}
-			break;
-		}
-		break;
-
-	default:
-		return (0);
-		break;
-	}
-
+        if (info->sector_count > CFG_MAX_FLASH_SECT) {
+            printf ("** ERROR: sector count %d > max (%d) **\n",
+            info->sector_count, CFG_MAX_FLASH_SECT);
+            info->sector_count = CFG_MAX_FLASH_SECT;
+        }
+									
 #if 0
 	/* check for protected sectors */
 	for (i = 0; i < info->sector_count; i++) {
diff -purN OLD/board/xsengine/fpga.c NEW/board/xsengine/fpga.c
--- OLD/board/xsengine/fpga.c	1970-01-01 01:00:00.000000000 +0100
+++ NEW/board/xsengine/fpga.c	2006-02-10 16:30:05.000000000 +0100
@@ -0,0 +1,270 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Spartan3 FPGA configuration support for the xsengine
+ */
+
+#include <common.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/arch/pxa-regs.h>
+#include "fpga.h"
+
+#if (CONFIG_FPGA)
+
+#ifdef FPGA_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define	PRINTF(fmt,args...)
+#endif
+
+/* Note that these are pointers to code that is in Flash.  They will be
+ * relocated at runtime.
+ */
+Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_init_fn,
+	fpga_err_fn,
+	fpga_done_fn,
+	fpga_clk_fn,
+	fpga_cs_fn,
+	fpga_wr_fn,
+	fpga_read_data_fn,
+	fpga_write_data_fn,
+	fpga_busy_fn,
+	fpga_abort_fn,
+	fpga_post_config_fn
+};
+
+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+	{ Xilinx_Spartan3,
+	  slave_parallel,
+	  CONFIG_FPGA_SIZE,
+	  (void *)&fpga_fns,
+	  0
+	}
+};
+
+/*
+ * Initialize the SelectMap interface.  We assume that the mode and the
+ * initial state of all of the port pins have already been set!
+ */
+void
+fpga_selectmap_init(void)
+{
+	PRINTF("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, __LINE__);
+	fpga_pgm_fn(FALSE, FALSE, 0);   /* make sure program pin is inactive */
+}
+
+
+/*
+ * Initialize the fpga.  Return 1 on success, 0 on failure.
+ */
+int
+xsengine_init_fpga(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int i;
+
+	PRINTF("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
+			__FUNCTION__, __LINE__, gd->reloc_off);
+	fpga_init(gd->reloc_off);
+	fpga_selectmap_init();
+
+	for(i=0; i < CONFIG_FPGA_COUNT; i++) {
+		PRINTF("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
+		fpga_add(fpga_xilinx, &fpga[i]);
+	}
+ 	return 1;
+}
+
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+int
+fpga_pgm_fn(int assert, int flush, int cookie)
+{
+	PRINTF("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
+
+	if (assert) {
+		GPCR0|=0x2000;
+		PRINTF("asserted\n");
+	}
+	else {
+		GPSR0|=0x2000;
+		PRINTF("deasserted\n");
+	}
+	return assert;
+}
+
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int
+fpga_done_fn(int cookie)
+{
+	PRINTF("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
+
+	if (GPLR0&0x4000) {
+		PRINTF("high\n");
+		return FPGA_SUCCESS;
+	}
+	else {
+		PRINTF("low\n");
+		return FPGA_FAIL;
+	}
+}
+
+
+/*
+ * Read FPGA SelectMap data.
+ */
+int
+fpga_read_data_fn(unsigned char *data, int cookie)
+{
+	vu_char *p = (vu_char *)CONFIG_FPGA_BASE;
+
+	*data = *p;
+#if 0
+	PRINTF("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int)data, data);
+#endif
+	return (int)data;
+}
+
+
+/*
+ * Write data to the FPGA SelectMap port
+ */
+int
+fpga_write_data_fn(unsigned char data, int flush, int cookie)
+{
+	vu_char *p = (vu_char *)CONFIG_FPGA_BASE;
+
+#if 0
+	PRINTF("%s: Write Data 0x%x\n", __FUNCTION__, (int)data);
+#endif
+	*p = data;
+	return (int)data;
+}
+
+
+/*
+ * Abort and FPGA operation
+ */
+int
+fpga_abort_fn(int cookie)
+{
+	PRINTF("%s:%d: FPGA program sequence aborted\n",
+		   __FUNCTION__, __LINE__);
+	return FPGA_FAIL;
+}
+
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int
+fpga_pre_config_fn(int cookie)
+{
+	PRINTF("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+	return 0;
+}
+
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+int
+fpga_post_config_fn(int cookie)
+{
+	PRINTF("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
+	return 0;
+}
+
+
+/*
+ * Clock, chip select and write signal are generated automatically by the
+ * cpu. The configuration check is based on the done signal that should 
+ * go high after the configuration.
+ */
+int
+fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	return assert_clk;
+}
+
+int
+fpga_cs_fn(int assert_cs, int flush, int cookie)
+{
+	return assert_cs;
+}
+
+int
+fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+	return assert_write;
+}
+
+int
+fpga_err_fn(int cookie)
+{
+	return 0;
+}
+
+int 
+fpga_busy_fn(int cookie)
+{
+	return 1;
+}
+
+int
+fpga_init_fn(int cookie)
+{
+	PRINTF("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
+
+	if (GPLR0&0x800) {
+		PRINTF("high\n");
+		return 0;
+	}
+	else {
+		PRINTF("low\n");
+		return 1;
+	}
+}
+
+void
+fpga_reset(int assert)
+{
+}
+
+#endif
diff -purN OLD/board/xsengine/fpga.h NEW/board/xsengine/fpga.h
--- OLD/board/xsengine/fpga.h	1970-01-01 01:00:00.000000000 +0100
+++ NEW/board/xsengine/fpga.h	2006-02-10 18:04:02.000000000 +0100
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Spartan3 FPGA configuration support for the xsengine board
+ */
+
+extern int xsengine_init_fpga(void);
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_err_fn(int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_read_data_fn(unsigned char *data, int cookie);
+extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
+extern int fpga_busy_fn(int cookie);
+extern int fpga_abort_fn(int cookie );
+extern int fpga_pre_config_fn(int cookie );
+extern int fpga_post_config_fn(int cookie );
diff -purN OLD/board/xsengine/Makefile NEW/board/xsengine/Makefile
--- OLD/board/xsengine/Makefile	2005-04-03 01:52:37.000000000 +0200
+++ NEW/board/xsengine/Makefile	2006-02-08 15:59:35.000000000 +0100
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= xsengine.o flash.o
+OBJS	:= xsengine.o flash.o fpga.o
 SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
diff -purN OLD/board/xsengine/xsengine.c NEW/board/xsengine/xsengine.c
--- OLD/board/xsengine/xsengine.c	2004-10-10 20:41:14.000000000 +0200
+++ NEW/board/xsengine/xsengine.c	2006-02-08 16:00:34.000000000 +0100
@@ -44,6 +44,10 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0xa0000100;
 
+#ifdef CONFIG_FPGA
+        xsengine_init_fpga();
+#endif
+	
 	return 0;
 }
 
diff -purN OLD/include/configs/xsengine.h NEW/include/configs/xsengine.h
--- OLD/include/configs/xsengine.h	2005-08-08 01:06:41.000000000 +0200
+++ NEW/include/configs/xsengine.h	2006-02-15 12:17:08.000000000 +0100
@@ -54,10 +54,9 @@
 
 /* FLASH organization */
 #define CFG_MAX_FLASH_BANKS		1		/* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT		128		/* max number of sectors on one chip    */
+#define CFG_MAX_FLASH_SECT		512		/* max number of sectors on one chip    */
 #define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
 #define PHYS_FLASH_2			0x00000000	/* Flash Bank #2 */
-#define PHYS_FLASH_SECT_SIZE		0x00020000	/* 127 KB sectors */
 #define CFG_FLASH_BASE			PHYS_FLASH_1
 
 /*
@@ -89,7 +88,7 @@
 #define CFG_FLASH_WRITE_TOUT		(50*CFG_HZ) 	/* Timeout for Flash Write */
 
 /* Size of malloc() pool */
-#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 256*1024)
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 1024*1024)
 #define CFG_GBL_DATA_SIZE		128		/* size in bytes reserved for initial data */
 
 /* Hardware drivers */
@@ -97,12 +96,20 @@
 #define CONFIG_SMC91111_BASE		0x04000300
 #define CONFIG_SMC_USE_32_BIT 		1
 
+#define CONFIG_FPGA                     CFG_XILINX_SPARTAN3
+#define CONFIG_FPGA_SIZE		XILINX_XC3S400_SIZE
+#define CONFIG_FPGA_BASE                0xC000000
+#define CONFIG_FPGA_BANK_SIZE           0x100000
+#define CFG_FPGA_WAIT                   (CFG_HZ/100)
+#define CONFIG_FPGA_COUNT               1
+#define CFG_FPGA_PROG_FEEDBACK          1
+
 /* select serial console configuration */
 #define CONFIG_FFUART			1
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_BAUDRATE			115200
-#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2)
+#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2 | CFG_CMD_FPGA)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -111,8 +118,8 @@
 #define CONFIG_ETHADDR			FF:FF:FF:FF:FF:FF
 #define CONFIG_NETMASK			255.255.255.0
 #define CONFIG_IPADDR			192.168.1.50
-#define CONFIG_SERVERIP			192.168.1.2
-#define CONFIG_BOOTARGS			"root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
+#define CONFIG_SERVERIP			192.168.1.1
+#define CONFIG_BOOTARGS			"root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS0,115200"
 #define CONFIG_CMDLINE_TAG
 
 /* Miscellaneous configurable options */
@@ -177,7 +184,7 @@
 #define CFG_ICMR_VAL			0x00000000	/* No interrupts enabled        */
 
 /* Memory settings */
-#define CFG_MSC0_VAL			0x25F425F0
+#define CFG_MSC0_VAL			0x12242390
 
 /* MDCNFG: SDRAM Configuration Register */
 #define CFG_MDCNFG_VAL			0x000009C9
diff -purN OLD/include/flash.h NEW/include/flash.h
--- OLD/include/flash.h	2005-12-22 01:53:50.000000000 +0100
+++ NEW/include/flash.h	2006-02-13 10:32:30.000000000 +0100
@@ -208,6 +208,12 @@ extern void flash_read_factory_serial(fl
 #define AMD_ID_GL064M_3 0x22012201	/* 3rd ID word for S29GL064M-R6 */
 #define AMD_ID_GL064MT_2 0x22102210	/* 2nd ID word for S29GL064M-R3 (top boot sector) */
 #define AMD_ID_GL064MT_3 0x22012201	/* 3rd ID word for S29GL064M-R3 (top boot sector) */
+#define AMD_ID_GL128N_2 0x22212221	/* 2nd ID word for S29GL128N */
+#define AMD_ID_GL128N_3 0x22012201	/* 3rd ID word for S29GL128N */
+#define AMD_ID_GL256N_2 0x22222222	/* 2nd ID word for S29GL256N */
+#define AMD_ID_GL256N_3 0x22012201	/* 3rd ID word for S29GL256N */
+#define AMD_ID_GL512N_2 0x22232223	/* 2nd ID word for S29GL512N */
+#define AMD_ID_GL512N_3 0x22012201	/* 3rd ID word for S29GL512N */
 
 #define AMD_ID_LV320B_2 0x221A221A	/* 2d ID word for AM29LV320MB at 0x38 */
 #define AMD_ID_LV320B_3 0x22002200	/* 3d ID word for AM29LV320MB at 0x3c */
@@ -407,6 +413,9 @@ extern void flash_read_factory_serial(fl
 #define FLASH_FUJLV650	0x00D0		/* Fujitsu MBM 29LV650UE/651UE		*/
 #define FLASH_MT28S4M16LC 0x00E1	/* Micron MT28S4M16LC			*/
 #define FLASH_S29GL064M 0x00F0		/* Spansion S29GL064M-R6		*/
+#define FLASH_S29GL128N 0x00F1		/* Spansion S29GL128N   		*/
+#define FLASH_S29GL256N 0x00F2		/* Spansion S29GL256N   		*/
+#define FLASH_S29GL512N 0x00F3		/* Spansion S29GL512N   		*/
 
 #define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
 
