
22 Aug
2020
22 Aug
'20
5:09 p.m.
On Mon, 17 Aug 2020 at 01:08, Stefan Roese sr@denx.de wrote:
From: Suneel Garapati sgarapati@marvell.com
Enable PCI memory regions in ranges property to be of multiple entry. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on PCI bus.
Signed-off-by: Suneel Garapati sgarapati@marvell.com Cc: Simon Glass sjg@chromium.org Cc: Bin Meng bmeng.cn@gmail.com
Signed-off-by: Stefan Roese sr@denx.de
Changes in v2:
- Add sandbox test
Changes in v1:
- Change patch subject
- Enhance Kconfig help descrition
- Use if() instead of #if
arch/sandbox/dts/test.dts | 5 +++-- configs/sandbox_defconfig | 1 + drivers/pci/Kconfig | 10 ++++++++++ drivers/pci/pci-uclass.c | 9 ++++++--- test/dm/pci.c | 22 ++++++++++++++++++++++ 5 files changed, 42 insertions(+), 5 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org