32-bit wide ECC memory modules report 40-bit width. Changed the DIMM data bus width test to 'less than 64' instead of 'equal 32'.
Signed-off-by: Lee Nipper lee.nipper@freescale.com --- cpu/mpc83xx/spd_sdram.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 0acca47..4ad5a3f 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -598,7 +598,7 @@ long int spd_sdram() debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
/* Check DIMM data bus width */ - if (spd.dataw_lsb == 0x20) { + if (spd.dataw_lsb < 64) { if (spd.mem_type == SPD_MEMTYPE_DDR) burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ else @@ -760,7 +760,7 @@ long int spd_sdram() sdram_cfg |= SDRAM_CFG_RD_EN;
/* The DIMM is 32bit width */ - if (spd.dataw_lsb == 0x20) { + if (spd.dataw_lsb < 64) { if (spd.mem_type == SPD_MEMTYPE_DDR) sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE; if (spd.mem_type == SPD_MEMTYPE_DDR2)