
29 Jun
2017
29 Jun
'17
7:38 p.m.
Hi Michal,
can you / did you send this to the kernel ML, too?
On Thu, Jun 29, 2017 at 3:14 AM, Michal Simek michal.simek@xilinx.com wrote:
This will simplify dt overlay structure for the whole PL.
Signed-off-by: Michal Simek michal.simek@xilinx.com
Reviewed-by: Moritz Fischer moritz.fischer@ettus.com
arch/arm/dts/zynq-7000.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 34fc6e5f8936..f993e19ef280 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -38,6 +38,14 @@ }; };
fpga_full: fpga-full {
compatible = "fpga-region";
fpga-mgr = <&devcfg>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>;
-- 1.9.1
Thanks,
Moritz