This is defined in the device tree in Linux. Copy over the settings so that this can be used instead of hard-coding the reset line.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/dts/rk3288-veyron.dtsi | 15 +++++++++++---- configs/chromebook_jerry_defconfig | 1 + include/configs/rk3288_common.h | 1 + 3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 7e37158..12404ff 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -106,6 +106,13 @@ priority = /bits/ 8 <200>; };
+ emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + }; + sound { compatible = "rockchip,rockchip-audio-max98090"; rockchip,model = "ROCKCHIP-I2S"; @@ -259,11 +266,12 @@ bus-width = <8>; cap-mmc-highspeed; mmc-hs200-1_8v; + mmc-pwrseq = <&emmc_pwrseq>; disable-wp; non-removable; num-slots = <1>; pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_deassert_reset>; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>; status = "okay"; };
@@ -671,9 +679,8 @@ };
emmc { - /* Make sure eMMC is not in reset */ - emmc_deassert_reset: emmc-deassert-reset { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_up>; + emmc_reset: emmc-reset { + rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; };
/* diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 39cd9d6..456b6ea 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_SPL_LED=y CONFIG_LED_GPIO=y +CONFIG_PWRSEQ=y CONFIG_RESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 238711a..f47573b 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -26,6 +26,7 @@ #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT