Re: [PATCH] riscv: ae350: Enable CCTL_SUEN

On Wed, Dec 21, 2022 at 11:00 AM Rick Chen rick@andestech.com wrote:

CCTL operations are available to Supervisor/User-mode software under the control of the mcache_ctl.CCTL_SUEN control bit. Enable it to support Superviosr(and User)

typo: Supervisor

CCTL operations.

Signed-off-by: Rick Chen rick@andestech.com

arch/riscv/cpu/ax25/cpu.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index c4c2de2ef0..fc3239e1ac 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -17,11 +17,13 @@

#define V5_MCACHE_CTL_IC_EN_OFFSET 0 #define V5_MCACHE_CTL_DC_EN_OFFSET 1 +#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8

nits: alignment seems wrong

#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19 #define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20

#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET) #define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET) +#define V5_MCACHE_CTL_CCTL_SUEN BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET)

nits: alignment seems wrong

#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET) #define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)

@@ -55,6 +57,8 @@ void harts_early_init(void) mcache_ctl_val |= V5_MCACHE_CTL_IC_EN; if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN)) mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;

•           if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
  

•                   mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
            csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
  
            /*
  

--

Regards, Bin