Signed-off-by: Anton Staaf robotboy@chromium.org Cc: Mike Frysinger vapier@gentoo.org Cc: Lukasz Majewski l.majewski@samsung.com Cc: Michal Simek monstr@monstr.eu --- arch/microblaze/include/asm/cache.h | 37 +++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) create mode 100644 arch/microblaze/include/asm/cache.h
diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h new file mode 100644 index 0000000..0373e88 --- /dev/null +++ b/arch/microblaze/include/asm/cache.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MICROBLAZE_CACHE_H__ +#define __MICROBLAZE_CACHE_H__ + +/* + * The microblaze can have either a 4 or 16 byte cacheline depending on whether + * you are using OPB(4) or CacheLink(16). If the board config has not specified + * a cacheline size we assume the larger value of 16 bytes for DMA buffer + * alignment. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 16 +#endif + +#endif /* __MICROBLAZE_CACHE_H__ */