BCM4912 is a Broadcom B53 based WLAN AP router SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family so it's added under ARCH_BCMBCA platform. This initial support includes a bare-bone implementation and dts with CPU subsystem, memory and ARM PL011 uart.
This SoC is supported in the linux-next git repository so the dts and dtsi files are copied from linux.
The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there to the console.
Signed-off-by: William Zhang william.zhang@broadcom.com ---
MAINTAINERS | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/bcm4912.dtsi | 128 +++++++++++++++++++++++ arch/arm/dts/bcm94912.dts | 30 ++++++ arch/arm/mach-bcmbca/Kconfig | 8 ++ arch/arm/mach-bcmbca/Makefile | 1 + arch/arm/mach-bcmbca/bcm4912/Kconfig | 17 +++ arch/arm/mach-bcmbca/bcm4912/Makefile | 5 + arch/arm/mach-bcmbca/bcm4912/mmu_table.c | 32 ++++++ board/broadcom/bcmbca/Kconfig | 7 ++ configs/bcm94912_defconfig | 23 ++++ include/configs/bcm94912.h | 11 ++ 12 files changed, 265 insertions(+) create mode 100644 arch/arm/dts/bcm4912.dtsi create mode 100644 arch/arm/dts/bcm94912.dts create mode 100644 arch/arm/mach-bcmbca/bcm4912/Kconfig create mode 100644 arch/arm/mach-bcmbca/bcm4912/Makefile create mode 100644 arch/arm/mach-bcmbca/bcm4912/mmu_table.c create mode 100644 configs/bcm94912_defconfig create mode 100644 include/configs/bcm94912.h
diff --git a/MAINTAINERS b/MAINTAINERS index 9a4751153524..65a6b1b21e77 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -219,6 +219,7 @@ F: board/broadcom/bcmbca/ F: drivers/timer/bcmbca-timer.c N: bcmbca N: bcm[9]?47622 +N: bcm[9]?4912 N: bcm[9]?63138 N: bcm[9]?63146 N: bcm[9]?63148 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f0615aba4960..74442b30f4d7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1165,6 +1165,8 @@ dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
dtb-$(CONFIG_BCM47622) += \ bcm947622.dtb +dtb-$(CONFIG_BCM4912) += \ + bcm94912.dtb dtb-$(CONFIG_BCM63138) += \ bcm963138.dtb dtb-$(CONFIG_BCM63146) += \ diff --git a/arch/arm/dts/bcm4912.dtsi b/arch/arm/dts/bcm4912.dtsi new file mode 100644 index 000000000000..3d016c2ce675 --- /dev/null +++ b/arch/arm/dts/bcm4912.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm4912", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm94912.dts b/arch/arm/dts/bcm94912.dts new file mode 100644 index 000000000000..a3623e6f6919 --- /dev/null +++ b/arch/arm/dts/bcm94912.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm4912.dtsi" + +/ { + model = "Broadcom BCM94912 Reference Board"; + compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 932fa19df810..acdb6defd8bf 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -12,6 +12,13 @@ config BCM47622 select DM_SERIAL select PL01X_SERIAL
+config BCM4912 + bool "Support for Broadcom 4912 Family" + select ARM64 + select SYS_ARCH_TIMER + select DM_SERIAL + select PL01X_SERIAL + config BCM63138 bool "Support for Broadcom 63138 Family" select TIMER @@ -63,6 +70,7 @@ config BCM6878 select PL01X_SERIAL
source "arch/arm/mach-bcmbca/bcm47622/Kconfig" +source "arch/arm/mach-bcmbca/bcm4912/Kconfig" source "arch/arm/mach-bcmbca/bcm63138/Kconfig" source "arch/arm/mach-bcmbca/bcm63146/Kconfig" source "arch/arm/mach-bcmbca/bcm63148/Kconfig" diff --git a/arch/arm/mach-bcmbca/Makefile b/arch/arm/mach-bcmbca/Makefile index e177b6298b24..e9c96605b506 100644 --- a/arch/arm/mach-bcmbca/Makefile +++ b/arch/arm/mach-bcmbca/Makefile @@ -4,6 +4,7 @@ #
obj-$(CONFIG_BCM47622) += bcm47622/ +obj-$(CONFIG_BCM4912) += bcm4912/ obj-$(CONFIG_BCM63138) += bcm63138/ obj-$(CONFIG_BCM63146) += bcm63146/ obj-$(CONFIG_BCM63148) += bcm63148/ diff --git a/arch/arm/mach-bcmbca/bcm4912/Kconfig b/arch/arm/mach-bcmbca/bcm4912/Kconfig new file mode 100644 index 000000000000..b8c14d1dc1a1 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm4912/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM4912 + +config TARGET_BCM94912 + bool "Broadcom 4912 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm4912" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm4912/Makefile b/arch/arm/mach-bcmbca/bcm4912/Makefile new file mode 100644 index 000000000000..62624977034b --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm4912/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj-y += mmu_table.o diff --git a/arch/arm/mach-bcmbca/bcm4912/mmu_table.c b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c new file mode 100644 index 000000000000..52a53a2c76d0 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Broadcom Ltd. + */ +#include <common.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> + +static struct mm_region bcm94912_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 1UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + /* SoC peripheral */ + .virt = 0xff800000UL, + .phys = 0xff800000UL, + .size = 0x100000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bcm94912_mem_map; diff --git a/board/broadcom/bcmbca/Kconfig b/board/broadcom/bcmbca/Kconfig index 6beb1417348d..7bdd96b68f84 100644 --- a/board/broadcom/bcmbca/Kconfig +++ b/board/broadcom/bcmbca/Kconfig @@ -16,6 +16,13 @@ config SYS_CONFIG_NAME
endif
+if TARGET_BCM94912 + +config SYS_CONFIG_NAME + default "bcm94912" + +endif + if TARGET_BCM963138
config SYS_CONFIG_NAME diff --git a/configs/bcm94912_defconfig b/configs/bcm94912_defconfig new file mode 100644 index 000000000000..355f10a3aaba --- /dev/null +++ b/configs/bcm94912_defconfig @@ -0,0 +1,23 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=50000000 +CONFIG_ARCH_BCMBCA=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_BCM4912=y +CONFIG_TARGET_BCM94912=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="bcm94912" +CONFIG_IDENT_STRING=" Broadcom BCM4912" +CONFIG_SYS_LOAD_ADDR=0x01000000 +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_CMD_CACHE=y +CONFIG_OF_EMBED=y +CONFIG_CLK=y diff --git a/include/configs/bcm94912.h b/include/configs/bcm94912.h new file mode 100644 index 000000000000..f3d17ddaacfb --- /dev/null +++ b/include/configs/bcm94912.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2022 Broadcom Ltd. + */ + +#ifndef __BCM94912_H +#define __BCM94912_H + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +#endif