We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER(). This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 - arch/powerpc/cpu/mpc85xx/cpu_init.c | 13 +++------- arch/powerpc/cpu/mpc85xx/fdt.c | 11 +++----- arch/powerpc/cpu/mpc85xx/p2041_serdes.c | 4 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 39 +---------------------------- arch/powerpc/include/asm/processor.h | 41 +----------------------------- 6 files changed, 13 insertions(+), 97 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index d7a62e9..35c2b1a 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -33,9 +33,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (IS_SVR_REV(svr, 1, 0)) { switch (SVR_SOC_VER(svr)) { case SVR_P1013: - case SVR_P1013_E: case SVR_P1022: - case SVR_P1022_E: puts("Work-around for Erratum SATA A001 enabled\n"); } } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 3637972..50ee506 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -356,8 +356,7 @@ int cpu_init_r(void) break; case 0x1: if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) { + ver == SVR_8541 || ver == SVR_8555) { puts("128 KB "); /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ cache_ctl = 0xc4000000; @@ -368,8 +367,7 @@ int cpu_init_r(void) break; case 0x2: if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) { + ver == SVR_8541 || ver == SVR_8555) { puts("256 KB "); /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ cache_ctl = 0xc8000000; @@ -405,8 +403,7 @@ int cpu_init_r(void) puts("enabled\n"); } #elif defined(CONFIG_BACKSIDE_L2_CACHE) - if ((SVR_SOC_VER(svr) == SVR_P2040) || - (SVR_SOC_VER(svr) == SVR_P2040_E)) { + if (SVR_SOC_VER(svr) == SVR_P2040) { puts("N/A\n"); goto skip_l2; } @@ -508,9 +505,7 @@ skip_l2: */ if (IS_SVR_REV(svr, 1, 0) && ((SVR_SOC_VER(svr) == SVR_P1022) || - (SVR_SOC_VER(svr) == SVR_P1022_E) || - (SVR_SOC_VER(svr) == SVR_P1013) || - (SVR_SOC_VER(svr) == SVR_P1013_E))) { + (SVR_SOC_VER(svr) == SVR_P1013))) { fsl_sata_reg_t *reg;
/* first SATA controller */ diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 977770e..21c3ad4 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -139,16 +139,14 @@ static inline u32 l2cache_size(void) break; case 0x1: if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) + ver == SVR_8541 || ver == SVR_8555) return 128; else return 256; break; case 0x2: if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) + ver == SVR_8541 || ver == SVR_8555) return 256; else return 512; @@ -231,8 +229,7 @@ static inline void ft_fixup_l2cache(void *blob) int has_l2 = 1;
/* P2040/P2040E has no L2, so dont set any L2 props */ - if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || - (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) + if (SVR_SOC_VER(get_svr()) == SVR_P2040) has_l2 = 0;
size = (l2cfg0 & 0x3fff) * 64 * 1024; @@ -407,7 +404,7 @@ static void ft_fixup_qe_snum(void *blob) unsigned int svr;
svr = mfspr(SPRN_SVR); - if (SVR_SOC_VER(svr) == SVR_8569_E) { + if (SVR_SOC_VER(svr) == SVR_8569) { if(IS_SVR_REV(svr, 1, 0)) do_fixup_by_compat_u32(blob, "fsl,qe", "fsl,qe-num-snums", 46, 1); diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c index f68f281..eec4ffe 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c @@ -78,7 +78,7 @@ enum srds_prtcl serdes_get_prtcl(int cfg, int lane) prtcl = serdes_cfg_tbl[cfg][lane];
/* P2040[e] does not support XAUI */ - if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + if (ver == SVR_P2040 && prtcl == XAUI_FM1) prtcl = NONE;
return prtcl; @@ -94,7 +94,7 @@ int is_serdes_prtcl_valid(u32 prtcl) return 0;
/* P2040[e] does not support XAUI */ - if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + if (ver == SVR_P2040 && prtcl == XAUI_FM1) return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) { diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 0365ca8..1d39b17 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -37,82 +37,45 @@ DECLARE_GLOBAL_DATA_PTR; struct cpu_type cpu_type_list [] = { #if defined(CONFIG_MPC85xx) CPU_TYPE_ENTRY(8533, 8533, 1), - CPU_TYPE_ENTRY(8533, 8533_E, 1), CPU_TYPE_ENTRY(8535, 8535, 1), - CPU_TYPE_ENTRY(8535, 8535_E, 1), CPU_TYPE_ENTRY(8536, 8536, 1), - CPU_TYPE_ENTRY(8536, 8536_E, 1), CPU_TYPE_ENTRY(8540, 8540, 1), CPU_TYPE_ENTRY(8541, 8541, 1), - CPU_TYPE_ENTRY(8541, 8541_E, 1), CPU_TYPE_ENTRY(8543, 8543, 1), - CPU_TYPE_ENTRY(8543, 8543_E, 1), CPU_TYPE_ENTRY(8544, 8544, 1), - CPU_TYPE_ENTRY(8544, 8544_E, 1), CPU_TYPE_ENTRY(8545, 8545, 1), - CPU_TYPE_ENTRY(8545, 8545_E, 1), - CPU_TYPE_ENTRY(8547, 8547_E, 1), + CPU_TYPE_ENTRY(8547, 8547, 1), CPU_TYPE_ENTRY(8548, 8548, 1), - CPU_TYPE_ENTRY(8548, 8548_E, 1), CPU_TYPE_ENTRY(8555, 8555, 1), - CPU_TYPE_ENTRY(8555, 8555_E, 1), CPU_TYPE_ENTRY(8560, 8560, 1), CPU_TYPE_ENTRY(8567, 8567, 1), - CPU_TYPE_ENTRY(8567, 8567_E, 1), CPU_TYPE_ENTRY(8568, 8568, 1), - CPU_TYPE_ENTRY(8568, 8568_E, 1), CPU_TYPE_ENTRY(8569, 8569, 1), - CPU_TYPE_ENTRY(8569, 8569_E, 1), CPU_TYPE_ENTRY(8572, 8572, 2), - CPU_TYPE_ENTRY(8572, 8572_E, 2), CPU_TYPE_ENTRY(P1010, P1010, 1), - CPU_TYPE_ENTRY(P1010, P1010_E, 1), CPU_TYPE_ENTRY(P1011, P1011, 1), - CPU_TYPE_ENTRY(P1011, P1011_E, 1), CPU_TYPE_ENTRY(P1012, P1012, 1), - CPU_TYPE_ENTRY(P1012, P1012_E, 1), CPU_TYPE_ENTRY(P1013, P1013, 1), - CPU_TYPE_ENTRY(P1013, P1013_E, 1), - CPU_TYPE_ENTRY(P1014, P1014_E, 1), CPU_TYPE_ENTRY(P1014, P1014, 1), - CPU_TYPE_ENTRY(P1015, P1015_E, 1), CPU_TYPE_ENTRY(P1015, P1015, 1), - CPU_TYPE_ENTRY(P1016, P1016_E, 1), CPU_TYPE_ENTRY(P1016, P1016, 1), CPU_TYPE_ENTRY(P1017, P1017, 1), - CPU_TYPE_ENTRY(P1017, P1017_E, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), - CPU_TYPE_ENTRY(P1020, P1020_E, 2), CPU_TYPE_ENTRY(P1021, P1021, 2), - CPU_TYPE_ENTRY(P1021, P1021_E, 2), CPU_TYPE_ENTRY(P1022, P1022, 2), - CPU_TYPE_ENTRY(P1022, P1022_E, 2), CPU_TYPE_ENTRY(P1023, P1023, 2), - CPU_TYPE_ENTRY(P1023, P1023_E, 2), CPU_TYPE_ENTRY(P1024, P1024, 2), - CPU_TYPE_ENTRY(P1024, P1024_E, 2), CPU_TYPE_ENTRY(P1025, P1025, 2), - CPU_TYPE_ENTRY(P1025, P1025_E, 2), CPU_TYPE_ENTRY(P2010, P2010, 1), - CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), - CPU_TYPE_ENTRY(P2020, P2020_E, 2), CPU_TYPE_ENTRY(P2040, P2040, 4), - CPU_TYPE_ENTRY(P2040, P2040_E, 4), CPU_TYPE_ENTRY(P2041, P2041, 4), - CPU_TYPE_ENTRY(P2041, P2041_E, 4), CPU_TYPE_ENTRY(P3041, P3041, 4), - CPU_TYPE_ENTRY(P3041, P3041_E, 4), CPU_TYPE_ENTRY_MASK(P3060, P3060, 6, 0xf3), - CPU_TYPE_ENTRY_MASK(P3060, P3060_E, 6, 0xf3), CPU_TYPE_ENTRY(P4040, P4040, 4), - CPU_TYPE_ENTRY(P4040, P4040_E, 4), CPU_TYPE_ENTRY(P4080, P4080, 8), - CPU_TYPE_ENTRY(P4080, P4080_E, 8), CPU_TYPE_ENTRY(P5010, P5010, 1), - CPU_TYPE_ENTRY(P5010, P5010_E, 1), CPU_TYPE_ENTRY(P5020, P5020, 2), - CPU_TYPE_ENTRY(P5020, P5020_E, 2), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 4e32639..0ed1f46 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1036,7 +1036,7 @@ #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
/* Some parts define SVR[0:23] as the SOC version */ -#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/
/* whether MPC8xxxE (i.e. has SEC) */ #if defined(CONFIG_MPC85xx) @@ -1055,82 +1055,45 @@ */
#define SVR_8533 0x803400 -#define SVR_8533_E 0x803C00 #define SVR_8535 0x803701 -#define SVR_8535_E 0x803F01 #define SVR_8536 0x803700 -#define SVR_8536_E 0x803F00 #define SVR_8540 0x803000 #define SVR_8541 0x807200 -#define SVR_8541_E 0x807A00 #define SVR_8543 0x803200 -#define SVR_8543_E 0x803A00 #define SVR_8544 0x803401 -#define SVR_8544_E 0x803C01 #define SVR_8545 0x803102 -#define SVR_8545_E 0x803902 -#define SVR_8547_E 0x803901 +#define SVR_8547 0x803101 #define SVR_8548 0x803100 -#define SVR_8548_E 0x803900 #define SVR_8555 0x807100 -#define SVR_8555_E 0x807900 #define SVR_8560 0x807000 #define SVR_8567 0x807501 -#define SVR_8567_E 0x807D01 #define SVR_8568 0x807500 -#define SVR_8568_E 0x807D00 #define SVR_8569 0x808000 -#define SVR_8569_E 0x808800 #define SVR_8572 0x80E000 -#define SVR_8572_E 0x80E800 #define SVR_P1010 0x80F100 -#define SVR_P1010_E 0x80F900 #define SVR_P1011 0x80E500 -#define SVR_P1011_E 0x80ED00 #define SVR_P1012 0x80E501 -#define SVR_P1012_E 0x80ED01 #define SVR_P1013 0x80E700 -#define SVR_P1013_E 0x80EF00 #define SVR_P1014 0x80F101 -#define SVR_P1014_E 0x80F901 #define SVR_P1015 0x80E502 -#define SVR_P1015_E 0x80ED02 #define SVR_P1016 0x80E503 -#define SVR_P1016_E 0x80ED03 #define SVR_P1017 0x80F700 -#define SVR_P1017_E 0x80FF00 #define SVR_P1020 0x80E400 -#define SVR_P1020_E 0x80EC00 #define SVR_P1021 0x80E401 -#define SVR_P1021_E 0x80EC01 #define SVR_P1022 0x80E600 -#define SVR_P1022_E 0x80EE00 #define SVR_P1023 0x80F600 -#define SVR_P1023_E 0x80FE00 #define SVR_P1024 0x80E402 -#define SVR_P1024_E 0x80EC02 #define SVR_P1025 0x80E403 -#define SVR_P1025_E 0x80EC03 #define SVR_P2010 0x80E300 -#define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 -#define SVR_P2020_E 0x80EA00 #define SVR_P2040 0x821000 -#define SVR_P2040_E 0x821800 #define SVR_P2041 0x821001 -#define SVR_P2041_E 0x821801 #define SVR_P3041 0x821103 -#define SVR_P3041_E 0x821903 #define SVR_P3060 0x820002 -#define SVR_P3060_E 0x820802 #define SVR_P4040 0x820100 -#define SVR_P4040_E 0x820900 #define SVR_P4080 0x820000 -#define SVR_P4080_E 0x820800 #define SVR_P5010 0x822100 -#define SVR_P5010_E 0x822900 #define SVR_P5020 0x822000 -#define SVR_P5020_E 0x822800
#define SVR_8610 0x80A000 #define SVR_8641 0x809000