Dear Dave Aldridge,
In message 1318251753-23604-1-git-send-email-fovsoft@gmail.com you wrote:
The Cadence GEM is based on the MACB Ethernet controller but has a few small changes with regards to register and bitfield placement. This patch detects the presence of a GEM by reading the module ID register and setting a flag appropriately.
This handles the new HW address, USRIO and hash register base register locations in GEM.
Signed-off-by: Dave Aldridge fovsoft@gmail.com
...
--- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -71,6 +71,15 @@ #define MACB_TPQ 0x00bc #define MACB_USRIO 0x00c0 #define MACB_WOL 0x00c4 +#define MACB_MID 0x00fc
+/* GEM register offsets. */ +#define GEM_NCFGR 0x0004 +#define GEM_USRIO 0x000c +#define GEM_HRB 0x0080 +#define GEM_HRT 0x0084 +#define GEM_SA1B 0x0088 +#define GEM_SA1T 0x008C
NAK.
/* Register access macros */ #define macb_readl(port,reg) \ readl((port)->regs + MACB_##reg) #define macb_writel(port,reg,value) \ writel((value), (port)->regs + MACB_##reg) +#define gem_readl(port, reg) \
- __raw_readl((port)->regs + GEM_##reg)
+#define gem_writel(port, reg, value) \
- __raw_writel((value), (port)->regs + GEM_##reg)
NAK. We don't allow regoister accesses through base address + offset notation any more.
Please use a C struct instead.
Best regards,
Wolfgang Denk