On 07.03.2018 22:52, Marek Behún wrote:
Lane 0 supports SGMII1 and USB3. Lane 1 supports SGMII0 and PEX0. Lane 2 supports SATA0 and USB3.
This is needed for Armada 37xx.
Signed-off-by: Marek Behun marek.behun@nic.cz
arch/arm/dts/armada-37xx.dtsi | 5 +++-- drivers/phy/marvell/comphy_a3700.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index 690234234b..d0529637f4 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -284,8 +284,9 @@ compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; reg = <0x18300 0x28>, <0x1f300 0x3d000>;
mux-bitcount = <1>;max-lanes = <2>;
mux-bitcount = <4>;mux-lane-order = <1 0 2>;max-lanes = <3>; };
Again, please see my comment about upstream Linux DT bindings for the A37xx PHY properties.
Thanks, Stefan
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 1182842609..c665d6fde8 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -14,6 +14,38 @@
DECLARE_GLOBAL_DATA_PTR;
+struct comphy_mux_data a3700_comphy_mux_data[] = { +/* Lane 0 */
- {
4,{{ PHY_TYPE_UNCONNECTED, 0x0 },{ PHY_TYPE_SGMII1, 0x0 },{ PHY_TYPE_USB3_HOST0, 0x1 },{ PHY_TYPE_USB3_DEVICE, 0x1 }}- },
+/* Lane 1 */
- {
3,{{ PHY_TYPE_UNCONNECTED, 0x0},{ PHY_TYPE_SGMII0, 0x0},{ PHY_TYPE_PEX0, 0x1}}- },
+/* Lane 2 */
- {
4,{{ PHY_TYPE_UNCONNECTED, 0x0},{ PHY_TYPE_SATA0, 0x0},{ PHY_TYPE_USB3_HOST0, 0x1},{ PHY_TYPE_USB3_DEVICE, 0x1}}- },
+};
- struct sgmii_phy_init_data_fix { u16 addr; u16 value;
@@ -943,6 +975,10 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
debug_enter();
- /* Initialize PHY mux */
- chip_cfg->mux_data = a3700_comphy_mux_data;
- comphy_mux_init(chip_cfg, serdes_map, COMPHY_SEL_ADDR);
- for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count; lane++, comphy_map++) { debug("Initialize serdes number %d\n", lane);
Viele Grüße, Stefan