Hello,
Am 18.11.19 um 22:15 schrieb Simon Goldschmidt:
Am 18.11.2019 um 19:08 schrieb Wolfgang Grandegger:
Hello,
I'm trying to understand what is necessary to get mainline U-Boot booting from the eMMC of an Arria10 board, which is significantly different to the Cyclone 5.
Unfortunately, my playground here is limited to Cyclone 5, but from the U-Boot side and from what I know, booting an Arria 10 should be very similar to Cyclone5 (given that Stratix 10 and Agilex have a very much different boot flow).
Do you have vendor U-Boot running? If not, I suggest to first get that running. The step to mainline U-Boot should then hopefully not be too hard.
I trying to get the vendor U-Boot v2019.04 from [1] booting as described in [2]. Unfortunately the SDRAM calibration fails:
FPGA: Early Release Succeeded. wait_for_bit_le32: Timeout (reg= mask=1 wait_set=) c2s=00000000 s2c=00000040 nr0=00000620 nr1=00004847 nr2=00000000 dst=00000002 emif_reset interrupt cleared nr0=00000620 nr1=00004847 nr2=00000000 wait_for_bit_le32: Timeout (reg= mask=1 wait_set=) c2s=00000000 s2c=00000040 nr0=00000620 nr1=00004847 nr2=00000000 dst=00000002 emif_reset interrupt cleared nr0=00000620 nr1=00004847 nr2=00000000 ... Error: Could Not Calibrate SDRAM DDRCAL: Failed Trying to boot from MMC1
It seems, that the SDRAM is still not accessible after loading the periph image. Any idea what could cause that issue? It works fine after a soft-reset or if I load the full image via JTAG.
[1] https://github.com/altera-opensource/u-boot-socfpga/tree/socfpga_v2019.04 [2] https://rocketboards.org/foswiki/Documentation/BuildingBootloader
TIA.
Wolfgang