Hi Dave,
I believe it is timing issue. The BCSR read(#LOE) has not enough setup time. You may try the two solutions: (a) slow down local bus clock If you are using default configuration, the local bus clock is 66MHz. change the LCRR from div 4 to div 8 to make the local bus clock as 33MHz. you can find it in the MPC8349EMDS.h
(b) Tuning the #CS1 timing, such as change the OR1 from 0xFFFFE8F0 to 0xFFFFE9F7
Let us know the result.
Sorry for not getting back to you sooner, I've been out of touch for the last week.
Freescale support responded that they were able to reproduce the issue on their hardware. In case you are interested; the support person in question was Fedor, and the SR# is 1-458670791. (I don't expect you to work on this, I'm just providing the information in case you care to look at it).
I haven't talked in detail with Ira regarding the additional tests he performed after I left last week, however, I believe he changed the clock rates as you mentioned and the error still occurred.
Our work-around that just writes the correct reset value to BCSR[0] was sufficient to keep him working on productive code.
Since you were not able to reproduce the problem on your hardware, I'm interested to learn how you determined that the LOE# signal does not have enough setup time. Did you look at the placed-and-routed BCSR project to determine actual timing?
I have a copy of the Verilog code used in the BCSR, but not the Xilinx ISE project. I'll take a more detailed look at the code, but I won't be able to look at the timing, unless I ask SR for an ISE project. I'll let them get back to me with their solution before I go trying to get the project files. Hopefully the fix will be to update the BCSR, and I'll just have to build a Xilinx download cable, and use the free web version of ISE to update the CPLD.
Thanks for helping look at this issue.
Cheers, Dave