From: Vipul Kumar vipul.kumar@xilinx.com
This patch added support to read ITAP and OTAP delay values from the device tree. If the DT does not contain tap delay values, the predefined values will be used for the same.
Signed-off-by: Vipul Kumar vipul.kumar@xilinx.com Signed-off-by: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com --- - These bindings were sent to mainline but not accepted yet. --- board/xilinx/zynqmp/tap_delays.c | 195 ++++++----------------------------- drivers/mmc/zynq_sdhci.c | 217 ++++++++++++++++++++++++++++++++++++++- include/zynqmp_tap_delay.h | 5 +- 3 files changed, 249 insertions(+), 168 deletions(-)
diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c index c3ae357..3788d67 100644 --- a/board/xilinx/zynqmp/tap_delays.c +++ b/board/xilinx/zynqmp/tap_delays.c @@ -24,43 +24,12 @@ #define SD1_ITAPDLYENA_MASK 0x01000000 #define SD1_ITAPDLYENA 0x01000000 #define SD0_ITAPDLYSEL_MASK 0x000000FF -#define SD0_ITAPDLYSEL_HSD 0x00000015 -#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003D -#define SD0_ITAPDLYSEL_MMC_DDR50 0x00000012
#define SD1_ITAPDLYSEL_MASK 0x00FF0000 -#define SD1_ITAPDLYSEL_HSD 0x00150000 -#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000 -#define SD1_ITAPDLYSEL_MMC_DDR50 0x00120000
#define SD0_OTAPDLYSEL_MASK 0x0000003F -#define SD0_OTAPDLYSEL_MMC_HSD 0x00000006 -#define SD0_OTAPDLYSEL_SD_HSD 0x00000005 -#define SD0_OTAPDLYSEL_SDR50 0x00000003 -#define SD0_OTAPDLYSEL_SDR104_B0 0x00000003 -#define SD0_OTAPDLYSEL_SDR104_B2 0x00000002 -#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004 -#define SD0_OTAPDLYSEL_MMC_DDR50 0x00000006
#define SD1_OTAPDLYSEL_MASK 0x003F0000 -#define SD1_OTAPDLYSEL_MMC_HSD 0x00060000 -#define SD1_OTAPDLYSEL_SD_HSD 0x00050000 -#define SD1_OTAPDLYSEL_SDR50 0x00030000 -#define SD1_OTAPDLYSEL_SDR104_B0 0x00030000 -#define SD1_OTAPDLYSEL_SDR104_B2 0x00020000 -#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000 -#define SD1_OTAPDLYSEL_MMC_DDR50 0x00060000 - -#define MMC_BANK2 0x2 - -#define MMC_TIMING_UHS_SDR25 1 -#define MMC_TIMING_UHS_SDR50 2 -#define MMC_TIMING_UHS_SDR104 3 -#define MMC_TIMING_UHS_DDR50 4 -#define MMC_TIMING_MMC_HS200 5 -#define MMC_TIMING_SD_HS 6 -#define MMC_TIMING_MMC_DDR52 7 -#define MMC_TIMING_MMC_HS 8
void zynqmp_dll_reset(u8 deviceid) { @@ -81,149 +50,49 @@ void zynqmp_dll_reset(u8 deviceid) zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0); }
-static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank) -{ - if (deviceid == 0) { - /* Program OTAP */ - if (bank == MMC_BANK2) - zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_SDR104_B2); - else - zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_SDR104_B0); - } else { - /* Program OTAP */ - if (bank == MMC_BANK2) - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_SDR104_B2); - else - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_SDR104_B0); - } -} - -static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank) -{ - if (deviceid == 0) { - /* Program ITAP */ - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, - SD0_ITAPCHGWIN); - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK, - SD0_ITAPDLYENA); - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, - SD0_ITAPDLYSEL_HSD); - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0); - /* Program OTAP */ - if (timing == MMC_TIMING_MMC_HS) - zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_MMC_HSD); - else - zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_SD_HSD); - } else { - /* Program ITAP */ - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, - SD1_ITAPCHGWIN); - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK, - SD1_ITAPDLYENA); - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK, - SD1_ITAPDLYSEL_HSD); - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0); - /* Program OTAP */ - if (timing == MMC_TIMING_MMC_HS) - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_MMC_HSD); - else - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_SD_HSD); - } -} - -static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank) +void arasan_zynqmp_set_tapdelay(u8 deviceid, u32 itap_delay, u32 otap_delay) { if (deviceid == 0) { + zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, + SD0_DLL_RST); /* Program ITAP */ - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, - SD0_ITAPCHGWIN); - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK, - SD0_ITAPDLYENA); - if (timing == MMC_TIMING_UHS_DDR50) + if (itap_delay) { + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, + SD0_ITAPCHGWIN); + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK, + SD0_ITAPDLYENA); zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, - SD0_ITAPDLYSEL_SD_DDR50); - else - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, - SD0_ITAPDLYSEL_MMC_DDR50); - zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0); + itap_delay); + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, + 0x0); + } + /* Program OTAP */ - if (timing == MMC_TIMING_UHS_DDR50) + if (otap_delay) zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_SD_DDR50); - else - zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_MMC_DDR50); - } else { - /* Program ITAP */ - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, - SD1_ITAPCHGWIN); - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK, - SD1_ITAPDLYENA); - if (timing == MMC_TIMING_UHS_DDR50) - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK, - SD1_ITAPDLYSEL_SD_DDR50); - else - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK, - SD1_ITAPDLYSEL_MMC_DDR50); - zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0); - /* Program OTAP */ - if (timing == MMC_TIMING_UHS_DDR50) - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_SD_DDR50); - else - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_MMC_DDR50); - } -} + otap_delay);
-static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank) -{ - if (deviceid == 0) { - /* Program OTAP */ - zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, - SD0_OTAPDLYSEL_SDR50); + zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0); } else { - /* Program OTAP */ - zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, - SD1_OTAPDLYSEL_SDR50); - } -} - -void arasan_zynqmp_set_tapdelay(u8 deviceid, u8 timing, u8 bank) -{ - if (deviceid == 0) - zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, - SD0_DLL_RST); - else zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, SD1_DLL_RST); + /* Program ITAP */ + if (itap_delay) { + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, + SD1_ITAPCHGWIN); + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK, + SD1_ITAPDLYENA); + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK, + (itap_delay << 16)); + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, + 0x0); + }
- switch (timing) { - case MMC_TIMING_UHS_SDR25: - arasan_zynqmp_tap_hs(deviceid, timing, bank); - break; - case MMC_TIMING_UHS_SDR50: - arasan_zynqmp_tap_sdr50(deviceid, timing, bank); - break; - case MMC_TIMING_UHS_SDR104: - case MMC_TIMING_MMC_HS200: - arasan_zynqmp_tap_sdr104(deviceid, timing, bank); - break; - case MMC_TIMING_UHS_DDR50: - arasan_zynqmp_tap_ddr50(deviceid, timing, bank); - break; - } + /* Program OTAP */ + if (otap_delay) + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, + (otap_delay << 16));
- if (deviceid == 0) - zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0); - else zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0); + } } diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index b05334d..25d5688 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -14,9 +14,37 @@ #include <malloc.h> #include <sdhci.h> #include <zynqmp_tap_delay.h> +#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
+#define SDHCI_ITAPDLYSEL_SD_HSD 0x00000015 +#define SDHCI_ITAPDLYSEL_SDR25 0x00000015 +#define SDHCI_ITAPDLYSEL_SDR50 0x00000000 +#define SDHCI_ITAPDLYSEL_SDR104_B2 0x00000000 +#define SDHCI_ITAPDLYSEL_SDR104_B0 0x00000000 +#define SDHCI_ITAPDLYSEL_MMC_HSD 0x00000015 +#define SDHCI_ITAPDLYSEL_SD_DDR50 0x0000003D +#define SDHCI_ITAPDLYSEL_MMC_DDR52 0x00000012 +#define SDHCI_ITAPDLYSEL_MMC_HS200_B2 0x00000000 +#define SDHCI_ITAPDLYSEL_MMC_HS200_B0 0x00000000 +#define SDHCI_OTAPDLYSEL_SD_HSD 0x00000005 +#define SDHCI_OTAPDLYSEL_SDR25 0x00000005 +#define SDHCI_OTAPDLYSEL_SDR50 0x00000003 +#define SDHCI_OTAPDLYSEL_SDR104_B0 0x00000003 +#define SDHCI_OTAPDLYSEL_SDR104_B2 0x00000002 +#define SDHCI_OTAPDLYSEL_MMC_HSD 0x00000006 +#define SDHCI_OTAPDLYSEL_SD_DDR50 0x00000004 +#define SDHCI_OTAPDLYSEL_MMC_DDR52 0x00000006 +#define SDHCI_OTAPDLYSEL_MMC_HS200_B0 0x00000003 +#define SDHCI_OTAPDLYSEL_MMC_HS200_B2 0x00000002 + +#define MMC_BANK2 0x2 +#define SD_HS_BUS_SPEED 6 +#define MMC_DDR52_BUS_SPEED 7 +#define MMC_HS_BUS_SPEED 8 +#define MMC_MAX_BUS_SPEED 9 + struct arasan_sdhci_plat { struct mmc_config cfg; struct mmc mmc; @@ -25,6 +53,8 @@ struct arasan_sdhci_plat {
struct arasan_sdhci_priv { struct sdhci_host *host; + u32 itapdly[MMC_MAX_BUS_SPEED]; + u32 otapdly[MMC_MAX_BUS_SPEED]; u8 deviceid; u8 bank; u8 no_1p8; @@ -168,12 +198,189 @@ static void arasan_sdhci_set_tapdelay(struct sdhci_host *host) struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev); struct mmc *mmc = (struct mmc *)host->mmc; u8 uhsmode; + u32 itap_delay; + u32 otap_delay; +
uhsmode = mode2timing[mmc->selected_mode];
- if (uhsmode >= UHS_SDR25_BUS_SPEED) - arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode, - priv->bank); + if (uhsmode >= UHS_SDR25_BUS_SPEED) { + itap_delay = priv->itapdly[uhsmode]; + otap_delay = priv->otapdly[uhsmode]; + arasan_zynqmp_set_tapdelay(priv->deviceid, itap_delay, + otap_delay); + } +} + +/** + * arasan_zynqmp_dt_parse_tap_delays - Read Tap Delay values from DT + * + * Called at initialization to parse the values of Tap Delays. + * + * @dev: Pointer to our struct udevice. + */ +static void arasan_zynqmp_dt_parse_tap_delays(struct udevice *dev) +{ + struct arasan_sdhci_priv *priv = dev_get_priv(dev); + u32 *itapdly = priv->itapdly; + u32 *otapdly = priv->otapdly; + int ret; + + /* + * Read Tap Delay values from DT, if the DT does not contain the + * Tap Values then use the pre-defined values + */ + ret = dev_read_u32(dev, "xlnx,itap-delay-sd-hsd", + &itapdly[SD_HS_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for SD_HS_BUS_SPEED\n"); + itapdly[SD_HS_BUS_SPEED] = SDHCI_ITAPDLYSEL_SD_HSD; + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-sd-hsd", + &otapdly[SD_HS_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for SD_HS_BUS_SPEED\n"); + otapdly[SD_HS_BUS_SPEED] = SDHCI_OTAPDLYSEL_SD_HSD; + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-sdr25", + &itapdly[UHS_SDR25_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for UHS_SDR25_BUS_SPEED\n"); + itapdly[UHS_SDR25_BUS_SPEED] = SDHCI_ITAPDLYSEL_SDR25; + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-sdr25", + &otapdly[UHS_SDR25_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for UHS_SDR25_BUS_SPEED\n"); + otapdly[UHS_SDR25_BUS_SPEED] = SDHCI_OTAPDLYSEL_SDR25; + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-sdr50", + &itapdly[UHS_SDR50_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for UHS_SDR50_BUS_SPEED\n"); + itapdly[UHS_SDR50_BUS_SPEED] = SDHCI_ITAPDLYSEL_SDR50; + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-sdr50", + &otapdly[UHS_SDR50_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for UHS_SDR50_BUS_SPEED\n"); + otapdly[UHS_SDR50_BUS_SPEED] = SDHCI_OTAPDLYSEL_SDR50; + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-sd-ddr50", + &itapdly[UHS_DDR50_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for UHS_DDR50_BUS_SPEED\n"); + itapdly[UHS_DDR50_BUS_SPEED] = SDHCI_ITAPDLYSEL_SD_DDR50; + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-sd-ddr50", + &otapdly[UHS_DDR50_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for UHS_DDR50_BUS_SPEED\n"); + otapdly[UHS_DDR50_BUS_SPEED] = SDHCI_OTAPDLYSEL_SD_DDR50; + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-mmc-hsd", + &itapdly[MMC_HS_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for MMC_HS_BUS_SPEED\n"); + itapdly[MMC_HS_BUS_SPEED] = SDHCI_ITAPDLYSEL_MMC_HSD; + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-mmc-hsd", + &otapdly[MMC_HS_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for MMC_HS_BUS_SPEED\n"); + otapdly[MMC_HS_BUS_SPEED] = SDHCI_OTAPDLYSEL_MMC_HSD; + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-mmc-ddr52", + &itapdly[MMC_DDR52_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for MMC_DDR52_BUS_SPEED\n"); + itapdly[MMC_DDR52_BUS_SPEED] = SDHCI_ITAPDLYSEL_MMC_DDR52; + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-mmc-ddr52", + &otapdly[MMC_DDR52_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for MMC_DDR52_BUS_SPEED\n"); + otapdly[MMC_DDR52_BUS_SPEED] = SDHCI_OTAPDLYSEL_MMC_DDR52; + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-sdr104", + &itapdly[UHS_SDR104_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for UHS_SDR104_BUS_SPEED\n"); + if (priv->bank == MMC_BANK2) { + itapdly[UHS_SDR104_BUS_SPEED] = + SDHCI_ITAPDLYSEL_SDR104_B2; + } else { + itapdly[UHS_SDR104_BUS_SPEED] = + SDHCI_ITAPDLYSEL_SDR104_B0; + } + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-sdr104", + &otapdly[UHS_SDR104_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for UHS_SDR104_BUS_SPEED\n"); + if (priv->bank == MMC_BANK2) { + otapdly[UHS_SDR104_BUS_SPEED] = + SDHCI_OTAPDLYSEL_SDR104_B2; + } else { + otapdly[UHS_SDR104_BUS_SPEED] = + SDHCI_OTAPDLYSEL_SDR104_B0; + } + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-mmc-hs200", + &itapdly[MMC_HS200_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for MMC_HS200_BUS_SPEED\n"); + if (priv->bank == MMC_BANK2) { + itapdly[MMC_HS200_BUS_SPEED] = + SDHCI_ITAPDLYSEL_MMC_HS200_B2; + } else { + itapdly[MMC_HS200_BUS_SPEED] = + SDHCI_ITAPDLYSEL_MMC_HS200_B0; + } + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-mmc-hs200", + &otapdly[MMC_HS200_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for MMC_HS200_BUS_SPEED\n"); + if (priv->bank == MMC_BANK2) { + otapdly[MMC_HS200_BUS_SPEED] = + SDHCI_OTAPDLYSEL_MMC_HS200_B2; + } else { + otapdly[MMC_HS200_BUS_SPEED] = + SDHCI_OTAPDLYSEL_MMC_HS200_B0; + } + } }
static void arasan_sdhci_set_control_reg(struct sdhci_host *host) @@ -305,6 +512,10 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1); priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
+#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP) + arasan_zynqmp_dt_parse_tap_delays(dev); +#endif + plat->f_max = dev_read_u32_default(dev, "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ); return 0; diff --git a/include/zynqmp_tap_delay.h b/include/zynqmp_tap_delay.h index b07e3e0..7b71343 100644 --- a/include/zynqmp_tap_delay.h +++ b/include/zynqmp_tap_delay.h @@ -10,10 +10,11 @@
#ifdef CONFIG_ARCH_ZYNQMP void zynqmp_dll_reset(u8 deviceid); -void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank); +void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay, u32 otap_delay); #else inline void zynqmp_dll_reset(u8 deviceid) {} -inline void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank) {} +inline void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay, + u32 otap_delay) {} #endif
#endif