Building sun8i-emac for the A83T variant fail. This is due to different sunxi_ccm_reg members structures of R40 and H3 not present in A83T ones.
This patch fix this problem by adding some ifdef around thses problematic code.
Signed-off-by: Corentin Labbe clabbe.montjoie@gmail.com --- drivers/net/sun8i_emac.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index c9798445c7d..65b32c3b967 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -643,6 +643,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#if defined(CONFIG_MACH_SUN8I_H3) if (priv->variant == H3_EMAC) { /* Only H3/H5 have clock controls for internal EPHY */ if (priv->use_internal_phy) { @@ -655,8 +656,10 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) BIT(AHB_RESET_OFFSET_EPHY)); } } +#endif
if (priv->variant == R40_GMAC) { +#if defined(CONFIG_MACH_SUN8I_R40) /* Set clock gating for emac */ setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
@@ -669,6 +672,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) CCM_GMAC_CTRL_GPIT_RGMII); setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); +#endif } else { /* Set clock gating for emac */ setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));