
7 Sep
2012
7 Sep
'12
11:42 p.m.
Thierry,
On Mon, Jul 30, 2012 at 11:21 PM, Thierry Reding thierry.reding@avionic-design.de wrote:
In order for cache invalidation and flushing to work properly, the data and OOB buffers must be aligned to full cache lines.
Signed-off-by: Thierry Reding thierry.reding@avionic-design.de
This patch, along with the Tegra: 'Enable NAND on TEC' patch, applied to u-boot-tegra/next. Thanks!
Tom
common/cmd_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_nand.c b/common/cmd_nand.c index a91ccf4..4367f5a 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
last = off;
datbuf = malloc(nand->writesize);
oobbuf = malloc(nand->oobsize);
datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize); if (!datbuf || !oobbuf) { puts("No memory for page buffer\n"); return 1;
-- 1.7.11.3