From: Jeffy Chen jeffy.chen@rock-chips.com
Our chips may have different max spl size and spl header, so we need to add configs for that.
Signed-off-by: Jeffy Chen jeffy.chen@rock-chips.com Acked-by: Simon Glass sjg@chromium.org Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass sjg@chromium.org
---
Changes in v8: - Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, - Add $(if...) to tools/Makefile to fix widespread build breakage
arch/arm/mach-rockchip/Kconfig | 15 +++++++++++++++ arch/arm/mach-rockchip/rk3036/Kconfig | 6 ++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 6 ++++++ tools/Makefile | 8 +++++++- tools/rkcommon.c | 2 +- tools/rkcommon.h | 1 - tools/rkimage.c | 2 +- tools/rksd.c | 4 ++-- tools/rkspi.c | 4 ++-- 9 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6b608db..4848018 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -17,6 +17,21 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+config ROCKCHIP_SPL_HDR + string "Header of rockchip's spl loader" + help + Rockchip's bootrom requires the spl loader to start with a 4-bytes + header. The content of this header depends on the chip type. + +config ROCKCHIP_MAX_SPL_SIZE + hex "Max size of rockchip's spl loader" + help + Different chip may have different sram size. And if we want to jump + back to the bootrom after spl, we may need to reserve some sram space + for the bootrom. + The max spl loader size should be sram size minus reserved + size(if needed) + config SYS_MALLOC_F default y
diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index 0fbc58e..95fb2b9 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -9,6 +9,12 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400
+config ROCKCHIP_SPL_HDR + default "RK30" + +config ROCKCHIP_MAX_SPL_SIZE + default 0x1000 + config ROCKCHIP_COMMON bool "Support rk common fuction"
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index d0a7276..3de3878 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -16,6 +16,12 @@ config TARGET_CHROMEBOOK_JERRY WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions.
+config ROCKCHIP_SPL_HDR + default "RK32" + +config ROCKCHIP_MAX_SPL_SIZE + default 0x8000 + config SYS_SOC default "rockchip"
diff --git a/tools/Makefile b/tools/Makefile index 9082bda..117b07e 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -64,7 +64,7 @@ RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \ rsa-sign.o rsa-verify.o rsa-checksum.o \ rsa-mod-exp.o)
-ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o +ROCKCHIP_OBS = $(if $(CONFIG_ARCH_ROCKCHIP),lib/rc4.o rkcommon.o rkimage.o rksd.o,)
# common objs for dumpimage and mkimage dumpimage-mkimage-objs := aisimage.o \ @@ -108,6 +108,12 @@ fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o
# TODO(sjg@chromium.org): Is this correct on Mac OS?
+ifneq ($(CONFIG_ARCH_ROCKCHIP),) +HOST_EXTRACFLAGS += \ + -DCONFIG_ROCKCHIP_MAX_SPL_SIZE=$(CONFIG_ROCKCHIP_MAX_SPL_SIZE) \ + -DCONFIG_ROCKCHIP_SPL_HDR=""$(CONFIG_ROCKCHIP_SPL_HDR)"" +endif + ifneq ($(CONFIG_MX23)$(CONFIG_MX28),) # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register # the mxsimage support within tools/mxsimage.c . diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 4389622..18778aa 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -50,7 +50,7 @@ int rkcommon_set_header(void *buf, uint file_size) { struct header0_info *hdr;
- if (file_size > RK_MAX_CODE1_SIZE) + if (file_size > CONFIG_ROCKCHIP_MAX_SPL_SIZE) return -ENOSPC;
memset(buf, '\0', RK_CODE1_OFFSET * RK_BLK_SIZE); diff --git a/tools/rkcommon.h b/tools/rkcommon.h index 57fd726..39b1d52 100644 --- a/tools/rkcommon.h +++ b/tools/rkcommon.h @@ -11,7 +11,6 @@ enum { RK_BLK_SIZE = 512, RK_CODE1_OFFSET = 4, - RK_MAX_CODE1_SIZE = 32 << 10, };
/** diff --git a/tools/rkimage.c b/tools/rkimage.c index 7b292f4..73634e3 100644 --- a/tools/rkimage.c +++ b/tools/rkimage.c @@ -30,7 +30,7 @@ static void rkimage_print_header(const void *buf) static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd, struct image_tool_params *params) { - memcpy(buf, "RK32", 4); + memcpy(buf, CONFIG_ROCKCHIP_SPL_HDR, 4); }
static int rkimage_extract_subimage(void *buf, struct image_tool_params *params) diff --git a/tools/rksd.c b/tools/rksd.c index a8dbe98..30b149d 100644 --- a/tools/rksd.c +++ b/tools/rksd.c @@ -50,7 +50,7 @@ static void rksd_set_header(void *buf, struct stat *sbuf, int ifd, size); }
- memcpy(buf + RKSD_SPL_HDR_START, "RK32", 4); + memcpy(buf + RKSD_SPL_HDR_START, CONFIG_ROCKCHIP_SPL_HDR, 4); }
static int rksd_extract_subimage(void *buf, struct image_tool_params *params) @@ -72,7 +72,7 @@ static int rksd_vrec_header(struct image_tool_params *params, { int pad_size;
- pad_size = RKSD_SPL_HDR_START + RK_MAX_CODE1_SIZE; + pad_size = RKSD_SPL_HDR_START + CONFIG_ROCKCHIP_MAX_SPL_SIZE; debug("pad_size %x\n", pad_size);
return pad_size - params->file_size; diff --git a/tools/rkspi.c b/tools/rkspi.c index a3c4c73..13cc593 100644 --- a/tools/rkspi.c +++ b/tools/rkspi.c @@ -53,7 +53,7 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd, size); }
- memcpy(buf + RKSPI_SPL_HDR_START, "RK32", 4); + memcpy(buf + RKSPI_SPL_HDR_START, CONFIG_ROCKCHIP_SPL_HDR, 4);
/* * Spread the image out so we only use the first 2KB of each 4KB @@ -89,7 +89,7 @@ static int rkspi_vrec_header(struct image_tool_params *params, { int pad_size;
- pad_size = (RK_MAX_CODE1_SIZE + 0x7ff) / 0x800 * 0x800; + pad_size = (CONFIG_ROCKCHIP_MAX_SPL_SIZE + 0x7ff) / 0x800 * 0x800; params->orig_file_size = pad_size;
/* We will double the image size due to the SPI format */