Dear Detlev Zundel,
Hi Marek,
This reverts commit 69d26d09de1cb93e0a09ca71d9f0d41a66f0756a.
Apparently, this commit got mainline only because of OOT port and causes breakage on board that is mainline. Revert.
To be honest, I don't understand what this patch or what the original patch did, nor through what OOT port this hit mainline and what breakage it causes on other boards.
It enabled some additional address bits on X board, allowing it to use full 512MB of RAM. But because we don't have any other such configured board and X board isn't mainline, I reverted this patch. It caused trouble on new 256MB configuration of M28.
Once there'll be some module that needs different memory configuration (like X board) mainline, we'll add this here, but until then, I'd like to stick with common memory init.
So also I can read the sentence, I cannot make heads and tails of it. Can you please write commit messages that people like me can make some sense from? I.e. answering the following questions would help me
- What does the original commit do? (its too late to change the original commit)
Enabled additional address bits, to address full 512 MB of DRAM on the X board.
- Why was the change made in the first place and for what OOT port?
Change of a DRAM configuration register that enabled additional address bit, at address 512MB of DRAM. Though this caused memory hole on our M28 module with 256MB of DRAM, which _is_ mainline. X board is OOT and never will be mainlined I guess.
- What breakage is caused on what boards?
See above.
- Why can we revert the change without any problems?
Because we don't have any mainline port that used this feature.
Thanks Detlev
Best regards, Marek Vasut