On Friday 08 February 2008, Nikhil Gautam wrote:
I figured couple of more things that needed change
In ndfc.c #ifdef CFG_NAND_4_ADDR_CYCLE /* Set NandFlash Core Configuration Register */ /* 2 col x 2 rows */ out32(base + NDFC_CCR, 0x00002000 | (cs << 24)); #else /* Set NandFlash Core Configuration Register */ /* 1 col x 2 rows */ out32(base + NDFC_CCR, 0x00000000 | (cs << 24)); #endif /* CFG_NAND_4_ADDR_CYCLE */
I don't think this change is needed. This only affects "auto-read" mode, so the first stage NAND boot loader (IPL), that loads the 4k SPL which we are talking about right now into memory. But you have to configure the corresponding bits in the bootstrap EEPROM correctly of course.
Also for 1Gb NAND flash, the address fetch is different then 256Mb, here is what I changed
#ifdef CFG_NAND_4_ADDR_CYCLE /* Column address */ this->write_byte(mtd, 0); /* A[7:0] */ this->write_byte(mtd, (uchar)(page_addr & 0x0f)); /* A[11:8] */ this->write_byte(mtd, (uchar)((page_addr >> 4) & 0xff)); /* A[19:12] */ /* One more address cycle for devices > 32MiB */ this->write_byte(mtd, (uchar)((page_addr >> 12) & 0xff)); /* A[27:20] */ #else /* Column address */ this->write_byte(mtd, 0); /* A[7:0] */ this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */ this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */ #endif
This doesn't match the 4 address cycle mode used for bigger 512k page devices. I think we may need another config define for 2k page devices.
Even with these two changes, the board is not booting??
And where does it hang? Did you have a chance to see where execution stops? Is nand_boot() called at all?
I suggest to debug things extensively with an BDI2000.
Best regards, Stefan
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