On Wed, Apr 5, 2017 at 4:32 AM, Ley Foon Tan ley.foon.tan@intel.com wrote:
These registers only available for Gen5 device, exclude them from Arria 10 build.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
drivers/fpga/socfpga.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index f1b2f2c..3751574 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
static struct socfpga_fpga_manager *fpgamgr_regs = (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +#endif
The ordering of the patches is important. You shouldn't need this patch because in patch #17, you wrapped the CONFIG_FPGA_SOCFPGA define by a GEN5 build. So this shouldn't get compiled at all.
But then I had a comment as to why the need to remove the FPGA build for A10.
Dinh