Signed-off-by: Joe Hershberger joe.hershberger@ni.com Cc: Joe Hershberger joe.hershberger@gmail.com Cc: Kim Phillips kim.phillips@freescale.com --- include/configs/MERGERBOX.h | 14 +++++++------- include/configs/MPC8308RDB.h | 10 +++++----- include/configs/MPC8313ERDB.h | 10 +++++----- include/configs/MPC8315ERDB.h | 14 +++++++------- include/configs/MPC8323ERDB.h | 14 +++++++------- include/configs/MPC832XEMDS.h | 16 ++++++++-------- include/configs/MPC8349EMDS.h | 19 +++++++++---------- include/configs/MPC8349ITX.h | 14 +++++++------- include/configs/MPC8360EMDS.h | 18 +++++++++--------- include/configs/MPC8360ERDK.h | 18 +++++++++--------- include/configs/MPC837XEMDS.h | 18 +++++++++--------- include/configs/MPC837XERDB.h | 18 +++++++++--------- include/configs/MVBLM7.h | 13 ++++++------- include/configs/SIMPC8313.h | 12 ++++++------ include/configs/TQM834x.h | 16 ++++++++-------- include/configs/km/km83xx-common.h | 14 +++++++------- include/configs/kmeter1.h | 8 ++++---- include/configs/kmsupx5.h | 4 ++-- include/configs/mpc8308_p1m.h | 10 +++++----- include/configs/sbc8349.h | 14 +++++++------- include/configs/suvd3.h | 8 ++++---- include/configs/tuda1.h | 8 ++++---- include/configs/tuxa1.h | 8 ++++---- include/configs/ve8313.h | 12 ++++++------ include/configs/vme8349.h | 16 ++++++++-------- 25 files changed, 162 insertions(+), 164 deletions(-)
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h index 105a45a..15cd646 100644 --- a/include/configs/MERGERBOX.h +++ b/include/configs/MERGERBOX.h @@ -409,7 +409,7 @@ /* DDR: cache cacheable */ #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_10 |\ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_RW |\ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\ BATU_VP) @@ -423,7 +423,7 @@ #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 |\ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW |\ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\ BATU_VP) @@ -437,23 +437,23 @@ #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 |\ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\ BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 |\ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\ BATU_VS | BATU_VP) @@ -461,7 +461,7 @@ #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\ BATU_VS | BATU_VP) diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index e6b83c8..6a39cee 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -464,7 +464,7 @@ */
/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ BATU_VS | BATU_VP) @@ -472,7 +472,7 @@ #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ BATU_VP) @@ -480,17 +480,17 @@ #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index edcd085..dde03ee 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -562,20 +562,20 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP)
/* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ @@ -591,7 +591,7 @@
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ @@ -600,7 +600,7 @@ | BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT7L (0) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 62ecfdc..81a3491 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -577,7 +577,7 @@
/* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_128M \ @@ -588,7 +588,7 @@
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ @@ -600,20 +600,20 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ | BATU_BL_32M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \ | BATU_BL_128K \ | BATU_VS \ @@ -623,7 +623,7 @@
/* PCI MEM space: cacheable */ #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \ | BATU_BL_256M \ @@ -634,7 +634,7 @@
/* PCI MMIO space: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 957090d..a27d33c 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -460,7 +460,7 @@
/* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ @@ -471,7 +471,7 @@
/* IMMRBAR & PCI IO: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ @@ -483,14 +483,14 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ | BATU_BL_32M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U @@ -501,7 +501,7 @@ #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ | BATU_BL_128K \ | BATU_VS \ @@ -512,7 +512,7 @@ #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \ | BATU_BL_256M \ @@ -522,7 +522,7 @@ #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U /* PCI MMIO space: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 9e65b00..d276be4 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -483,7 +483,7 @@
/* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ @@ -494,7 +494,7 @@
/* IMMRBAR & PCI IO: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ @@ -506,7 +506,7 @@
/* BCSR: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ @@ -518,14 +518,14 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ | BATU_BL_32M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U @@ -536,7 +536,7 @@ #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ | BATU_BL_128K \ | BATU_VS \ @@ -547,7 +547,7 @@ #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ | BATU_BL_256M \ @@ -557,7 +557,7 @@ #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index b377650..f720797 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -633,7 +633,7 @@
/* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ @@ -643,14 +643,14 @@ /* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ @@ -666,14 +666,14 @@
#ifdef CONFIG_MPC83XX_PCI2 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ @@ -689,7 +689,7 @@
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ @@ -699,10 +699,9 @@
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ #define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_10 \ - | BATL_MEMCOHERENCE |\ - \ - BATL_GUARDEDSTORAGE) + | BATL_PP_RW \ + | BATL_MEMCOHERENCE \ + | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 \ | BATU_BL_256M \ | BATU_VS \ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index c98c675..8ad494f 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -648,7 +648,7 @@ boards, we say we have two, but don't display a message if we find only one. */
/* DDR */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ @@ -658,14 +658,14 @@ boards, we say we have two, but don't display a message if we find only one. */ /* PCI */ #ifdef CONFIG_PCI #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ @@ -681,14 +681,14 @@ boards, we say we have two, but don't display a message if we find only one. */
#ifdef CONFIG_MPC83XX_PCI2 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ @@ -704,7 +704,7 @@ boards, we say we have two, but don't display a message if we find only one. */
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ @@ -714,7 +714,7 @@ boards, we say we have two, but don't display a message if we find only one. */
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ #define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 \ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 5c6b1ac..3af4b9a 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -527,7 +527,7 @@
/* DDR/LBC SDRAM: cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ @@ -538,7 +538,7 @@
/* IMMRBAR & PCI IO: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ @@ -550,7 +550,7 @@
/* BCSR: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ @@ -562,21 +562,21 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ | BATU_BL_32M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* DDR/LBC SDRAM next 256M: cacheable */ #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \ | BATU_BL_256M \ @@ -586,7 +586,7 @@ #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ | BATU_BL_128K \ | BATU_VS \ @@ -597,7 +597,7 @@ #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ | BATU_BL_256M \ @@ -607,7 +607,7 @@ #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 33fb937..a5cba19 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -437,7 +437,7 @@
/* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ @@ -448,7 +448,7 @@
/* IMMRBAR & PCI IO: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ @@ -460,7 +460,7 @@
/* NAND: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \ @@ -472,21 +472,21 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ | BATU_BL_32M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* Stack in dcache: cacheable, no memory coherence */ #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \ - | BATL_PP_10) + | BATL_PP_RW) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ | BATU_BL_128K \ | BATU_VS \ @@ -495,7 +495,7 @@ #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \ @@ -508,7 +508,7 @@ #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ | BATU_BL_256M \ @@ -518,7 +518,7 @@ #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 6a6621f..c17cec9 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -569,7 +569,7 @@ extern int board_pci_host_broken(void); #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ | BATU_BL_256M \ @@ -579,7 +579,7 @@ extern int board_pci_host_broken(void); #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ | BATU_BL_256M \ @@ -590,7 +590,7 @@ extern int board_pci_host_broken(void);
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ @@ -602,7 +602,7 @@ extern int board_pci_host_broken(void);
/* BCSR: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ @@ -614,20 +614,20 @@ extern int board_pci_host_broken(void);
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ | BATU_BL_32M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ | BATU_BL_128K \ | BATU_VS \ @@ -638,7 +638,7 @@ extern int board_pci_host_broken(void); #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ | BATU_BL_256M \ @@ -648,7 +648,7 @@ extern int board_pci_host_broken(void); #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 405589d..a0f8085 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -576,7 +576,7 @@ #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ | BATU_BL_256M \ @@ -586,7 +586,7 @@ #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ | BATU_BL_256M \ @@ -597,7 +597,7 @@
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ @@ -609,7 +609,7 @@
/* L2 Switch: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ @@ -621,20 +621,20 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ | BATU_BL_32M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ | BATU_BL_128K \ | BATU_VS \ @@ -645,7 +645,7 @@ #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ | BATU_BL_256M \ @@ -655,7 +655,7 @@ #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 4b3917e..7e9c5f3 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -345,7 +345,7 @@
/* DDR */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ @@ -354,14 +354,14 @@
/* PCI */ #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ @@ -377,7 +377,7 @@
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ @@ -387,10 +387,9 @@
/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */ #define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE \ - | \ - BATL_GUARDEDSTORAGE) + | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 \ | BATU_BL_256M \ | BATU_VS \ diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 3c8f221..3eb6f65 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -448,26 +448,26 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \ - | BATL_PP_10) + | BATL_PP_RW) #define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP)
/* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE \ @@ -481,7 +481,7 @@
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ @@ -491,7 +491,7 @@
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ #define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 \ | BATU_BL_256M \ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 8b8c604..1abfbb2 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -425,14 +425,14 @@
/* DDR 0 - 512M */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ | BATU_BL_256M \ @@ -441,7 +441,7 @@
/* stack in DCACHE @ 512M (no backing mem) */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ | BATU_BL_128K \ @@ -451,14 +451,14 @@ /* PCI */ #ifdef CONFIG_PCI #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ @@ -466,7 +466,7 @@ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ @@ -484,7 +484,7 @@
/* IMMRBAR */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ @@ -494,7 +494,7 @@
/* FLASH */ #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index 2b1a84a..9d28d8e 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -242,7 +242,7 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) @@ -250,7 +250,7 @@ #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ | BATU_VP) @@ -258,25 +258,25 @@ #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 3ae171b..5f68dc9 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -151,22 +151,22 @@ */
/* PAXE: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#ifdef CONFIG_PCI /* PCI MEM space: cacheable */ -#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE) #define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_DBAT6L CFG_IBAT6L #define CFG_DBAT6U CFG_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_DBAT7L CFG_IBAT7L diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index f8cd8e0..ccc1561 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -74,11 +74,11 @@ OR_GPCM_EAD)
/* LPXF: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 635afec..ba71d9f 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -455,7 +455,7 @@ */
/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ BATU_VS | BATU_VP) @@ -463,7 +463,7 @@ #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ BATU_VP) @@ -471,17 +471,17 @@ #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index d6207dd..9a16e74 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -555,7 +555,7 @@
/* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ @@ -565,14 +565,14 @@ /* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ @@ -588,14 +588,14 @@
#ifdef CONFIG_MPC83XX_PCI2 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ @@ -611,7 +611,7 @@
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ @@ -621,7 +621,7 @@
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ #define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 0b59d51..5f2e1e3 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -85,19 +85,19 @@
/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h index 853c00a..7ae7d58 100644 --- a/include/configs/tuda1.h +++ b/include/configs/tuda1.h @@ -106,7 +106,7 @@ */ /* PAXG: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_10 | \ + BATL_PP_RW | \ BATL_MEMCOHERENCE) /* 512M should also include APP2... */ #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ @@ -114,21 +114,21 @@ BATU_VS | \ BATU_VP) #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_10 | \ + BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* PINC3: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_10 | \ + BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ BATU_BL_256M | \ BATU_VS | \ BATU_VP) #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_10 | \ + BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h index ceeb5a3..815c260 100644 --- a/include/configs/tuxa1.h +++ b/include/configs/tuxa1.h @@ -99,20 +99,20 @@ * MMU Setup */ /* LPXF: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* PINC2: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 9035383..8d3836d 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -423,7 +423,7 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ | BATU_VS \ @@ -431,13 +431,13 @@
#if defined(CONFIG_PCI) /* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | BATU_BL_256M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ @@ -459,7 +459,7 @@
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ @@ -468,11 +468,11 @@ | BATU_VP)
/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
/* FPGA, SRAM, NAND @ 0x60000000 */ -#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 6a34537..e043e04 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -465,18 +465,18 @@ #define CONFIG_HIGH_BATS /* High BATs supported */
/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP)
/* PCI @ 0x80000000 */ #ifdef CONFIG_PCI -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) @@ -488,11 +488,11 @@ #endif
#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) @@ -504,17 +504,17 @@ #endif
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#if (CONFIG_SYS_DDR_SIZE == 512) #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ - BATL_PP_10 | BATL_MEMCOHERENCE) + BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ BATU_BL_256M | BATU_VS | BATU_VP) #else