Hi Maxim,
By any chance do you happen to know when in sunxi history the SPI controller grew QuadSPI/DualSPI support? It'd probably be feature creep to have in this patch series, but since they don't look too hard to implement, I might be interested in taking a stab at supporting them.
On 5/19/23 07:40, Maxim Kiselev wrote:
These SoCs have two SPI controllers that are quite similar to the SPI on previous Allwinner SoCs. The main difference is that new SoCs don't have a clock divider (SPI_CCR register) inside SPI IP.
Instead SPI sample mode should be configured depending on the input clock.
For now SPI input clock source selection is not supported by this driver, and only HOSC@24MHz can be used as input clock. Therefore, according to the, manual we could change the SPI sample mode from delay half cycle(default) to normal.
This patch adds a quirk for this kind of SPI controllers
Signed-off-by: Maxim Kiselev bigunclemax@gmail.com
Tested-by: Sam Edwards CFSworks@gmail.com
Cheers, Sam