Current DDR setup easily causes memory corruption, this patch fixes it.
Also fix TIMING_CFG0_MRS_CYC definition.
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- include/configs/MPC8360ERDK.h | 48 ++++++++++++++++++++++++++++++---------- include/mpc83xx.h | 3 +- 2 files changed, 38 insertions(+), 13 deletions(-)
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 97797cc..ba25a59 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -89,8 +89,8 @@
#define CFG_83XX_DDR_USES_CS0
-#undef CONFIG_DDR_ECC /* support DDR ECC function */ -#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ +#define CONFIG_DDR_ECC /* support DDR ECC function */ +#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
/* * DDRCDR - DDR Control Driver Register @@ -104,20 +104,44 @@ */ #define CONFIG_DDR_II #define CFG_DDR_SIZE 256 /* MB */ -#define CFG_DDRCDR 0x80080001 #define CFG_DDR_CS0_BNDS 0x0000000f #define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) -#define CFG_DDR_TIMING_0 0x00330903 -#define CFG_DDR_TIMING_1 0x3835a322 -#define CFG_DDR_TIMING_2 0x00104909 -#define CFG_DDR_TIMING_3 0x00000000 -#define CFG_DDR_CLK_CNTL 0x02000000 + CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) +#define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN) +#define CFG_DDR_SDRAM_CFG2 0x00001000 +#define CFG_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CFG_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (1115 << SDRAM_INTERVAL_REFINT_SHIFT)) #define CFG_DDR_MODE 0x47800432 #define CFG_DDR_MODE2 0x8000c000 -#define CFG_DDR_INTERVAL 0x045b0100 -#define CFG_DDR_SDRAM_CFG 0x03000000 -#define CFG_DDR_SDRAM_CFG2 0x00001000 + +#define CFG_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CFG_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_30) | \ + ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \ + ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + ( 3 << TIMING_CFG1_WRREC_SHIFT) | \ + (10 << TIMING_CFG1_REFREC_SHIFT) | \ + ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + ( 3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CFG_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (0 << TIMING_CFG2_CPO_SHIFT)) + +#define CFG_DDR_TIMING_3 0x00000000
/* * Memory test diff --git a/include/mpc83xx.h b/include/mpc83xx.h index df052e3..20df166 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -880,7 +880,7 @@ #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 -#define TIMING_CFG0_MRS_CYC 0x00000F00 +#define TIMING_CFG0_MRS_CYC 0x0000000F #define TIMING_CFG0_MRS_CYC_SHIFT 0
/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 @@ -903,6 +903,7 @@ #define TIMING_CFG1_WRTORD_SHIFT 0 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ +#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 2.5 */
/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */