SPL/TPL share the same secure_timer_init(), update to use one copy source code and update to use CONFIG_ROCKCHIP_STIMER_BASE as base address.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
arch/arm/mach-rockchip/rk3399-board-spl.c | 19 +-------------- arch/arm/mach-rockchip/rk3399-board-tpl.c | 18 +------------- arch/arm/mach-rockchip/rk3399/rk3399.c | 29 +++++++++++++++++++++++ include/configs/rk3399_common.h | 1 + 4 files changed, 32 insertions(+), 35 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 2333694caa..38cd1b3df1 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -109,27 +109,10 @@ void spl_perform_fixups(struct spl_image_info *spl_image) "u-boot,spl-boot-device", boot_ofpath); }
-#define TIMER_CHN10_BASE 0xff8680a0 -#define TIMER_END_COUNT_L 0x00 -#define TIMER_END_COUNT_H 0x04 -#define TIMER_INIT_COUNT_L 0x10 -#define TIMER_INIT_COUNT_H 0x14 -#define TIMER_CONTROL_REG 0x1c - -#define TIMER_EN 0x1 -#define TIMER_FMODE (0 << 1) -#define TIMER_RMODE (1 << 1) - -void secure_timer_init(void) +__weak void secure_timer_init(void) { - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); - writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); }
- void board_init_f(ulong dummy) { struct udevice *dev; diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c index 4a301249b4..6b3e8ac1f4 100644 --- a/arch/arm/mach-rockchip/rk3399-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3399-board-tpl.c @@ -12,24 +12,8 @@ #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h>
-#define TIMER_CHN10_BASE 0xff8680a0 -#define TIMER_END_COUNT_L 0x00 -#define TIMER_END_COUNT_H 0x04 -#define TIMER_INIT_COUNT_L 0x10 -#define TIMER_INIT_COUNT_H 0x14 -#define TIMER_CONTROL_REG 0x1c - -#define TIMER_EN 0x1 -#define TIMER_FMODE (0 << 1) -#define TIMER_RMODE (1 << 1) - -void secure_timer_init(void) +__weak void secure_timer_init(void) { - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); - writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); }
void board_init_f(ulong dummy) diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index e1f9f8b8ef..007be81cc3 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -38,6 +38,35 @@ static struct mm_region rk3399_mem_map[] = {
struct mm_region *mem_map = rk3399_mem_map;
+#ifdef CONFIG_SPL_BUILD + +#define TIMER_END_COUNT_L 0x00 +#define TIMER_END_COUNT_H 0x04 +#define TIMER_INIT_COUNT_L 0x10 +#define TIMER_INIT_COUNT_H 0x14 +#define TIMER_CONTROL_REG 0x1c + +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +void secure_timer_init(void) +{ + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; + + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H); + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L); + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \ + TIMER_CONTROL_REG); +} +#endif + int dram_init_banksize(void) { size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index f31f2658bb..8df0180284 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -13,6 +13,7 @@ #define CONFIG_SKIP_LOWLEVEL_INIT
#define COUNTER_FREQUENCY 24000000 +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0
#define CONFIG_SYS_NS16550_MEM32