[PATCH RFC 1/4] clk: sunxi: Add PWM bus clock and reset

This is needed for the D1 PWM driver.

Signed-off-by: John Watts contact@jookia.org --- drivers/clk/sunxi/clk_d1.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/sunxi/clk_d1.c b/drivers/clk/sunxi/clk_d1.c index 9dae761de8..6577d86e0b 100644 --- a/drivers/clk/sunxi/clk_d1.c +++ b/drivers/clk/sunxi/clk_d1.c @@ -15,6 +15,8 @@ static struct ccu_clk_gate d1_gates[] = { [CLK_APB0] = GATE_DUMMY,

+ [CLK_BUS_PWM] = GATE(0x7ac, BIT(0)), + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), @@ -48,6 +50,8 @@ static struct ccu_clk_gate d1_gates[] = { };

static struct ccu_reset d1_resets[] = { + [RST_BUS_PWM] = RESET(0x7ac, BIT(16)), + [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), [RST_BUS_MMC1] = RESET(0x84c, BIT(17)), [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),