The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receive Compliance test failure for a 100mV threshold.
Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v4: Update commit message about register setting. Clean up the math in register setting. Redefine SQRXTUNE to make code clearer.
Change in v3: - none
Change in v2: In function erratum_a009798(): 1.Put a blank line after variable declaration.
arch/arm/cpu/armv7/ls102xa/Kconfig | 8 +++++++- arch/arm/cpu/armv7/ls102xa/soc.c | 11 +++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + 3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 599cc28249..f09766cf03 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -6,6 +6,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -56,7 +57,12 @@ config SYS_FSL_ERRATUM_A010315 config SYS_FSL_ERRATUM_A009008 bool help - Workaround for USB erratum A009008 + Workaround for USB PHY erratum A009008 + +config SYS_FSL_ERRATUM_A009798 + bool + help + Workaround for USB PHY erratum A009798
config SYS_FSL_SRDS_1 bool diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 0cdc625380..487b5cf0ec 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -72,6 +72,16 @@ static void erratum_a009008(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ }
+static void erratum_a009798(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009798 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4); + + val &= ~(SCFG_USB_SQRXTUNE_MASK << 23); + out_be32(scfg + SCFG_USB3PRM1CR / 4, val); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ +}
void s_init(void) { @@ -161,6 +171,7 @@ int arch_soc_init(void)
/* Erratum */ erratum_a009008(); + erratum_a009798();
return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index ba59f40382..5762d3308a 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -176,6 +176,7 @@ struct ccsr_gur { #define SCFG_BASE 0x01570000 #define SCFG_USB3PRM1CR 0x070 #define SCFG_USB_TXVREFTUNE 0x9 +#define SCFG_USB_SQRXTUNE_MASK 0x7
/* Supplemental Configuration Unit */ struct ccsr_scfg {