Hi Leonid,
On Friday 20 October 2006 08:30, Leonid wrote:
I'm trying to port u-boot for "Yosemite-like" board with AMCC PPC440EP CPU. The difference between this board and Yosemite itself is that it has 4 128M banks of DDR SDRAM instead of 2 and (which is probably more important) these chips are on DIMM module.
If you are using DIMM modules, please don't use the board specific DDR init code of the Yosemite, but the cpu specific DDR init code für DDR DIMM modules, like the other 440 AMCC eval boards do (e.g. ocotea, bamboo).
I think I've configured everything correct, see SDRAM registers block from BDI2000 config file below:
; Setup SDRAM Controller (DDR SDRAM) WDCR 0x10 0x00000082 ;Select SDRAM0_CLKTR
<snip>
However MRSC bit of SDRAM0_MCSTS register never gets set meaning SDRAM controller has never successfully completed the Mode Register Set Command. Attempts to read memory also fail (from BDI2000 itself and from u-boot where I've modified memory configuration of course).
Please modify your U-Boot configuration to use the cpu/ppc4xx/spd_sdram.c code. The following lines should be added to your board config file (with the correct I2C addresses of course):
/*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
That can be HW problem of course, but may be somebody can suggest any configuration problem leading to similar symptoms? Any ideas at all?
Yes, a HW problem is also possible. What termination are you using? Did you "clone" the HW design from some IBM/AMCC eval boards?
Best regards, Stefan