On 18 March 2016 at 07:06, Purna Chandra Mandal purna.mandal@microchip.com wrote:
PIC32 internal flash devices are parallel NOR flash divided into number of banks to allow erase-programming in one while fetch and execution continues on other. As the flash banks are memory mapped stored code can be executed directly from flash (XIP), also there is additional hardware logic to prefetch and cache contents to improve execution performance. These flash can also be used to store user data (like environment). Flash erase and programming are handled by on-chip NVM controller.
Driver implemented driver model but MTD is not really support.
Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com
Changes in v3:
- add driver model support but MTD is not implemented
Changes in v2:
- kconfig: add CONFIG_FLASH_PIC32 dependent on MACH_PIC32
- fix single/multi-line comment style
- simplify byte-stream-to-word in little-endian format
- replace virt_to_phys() with CPHYSADDR()
- separate flash ID definition in different patch
drivers/mtd/Kconfig | 7 + drivers/mtd/Makefile | 1 + drivers/mtd/pic32_flash.c | 444 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 452 insertions(+) create mode 100644 drivers/mtd/pic32_flash.c
Reviewed-by: Simon Glass sjg@chromium.org