s On 10/20/2016 06:06 AM, Wenbin song wrote:
The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit GIC400_ADDR_ALIGN_64K[GIC_ADDR] is used to choose which offset will be used.
There seems to be a mismatch between the commit message and the actual macro used in the change. Also the message doesn't mention the implementation of smp_kick_all_cpu.
If GIC_ADDR bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting.
Signed-off-by: Wenbin Song wenbin.song@nxp.com Signed-off-by: Mingkai Hu mingkai.hu@nxp.com
v2: None
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 47 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 12 +++++- 2 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5d0b7a4..569d2c2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -14,6 +14,40 @@ #include <asm/arch/mp.h> #endif
+#ifdef CONFIG_LS1043A
It may be better to use a new Kconfig option such as HAS_FEATURE_XYZ, in case a future SoC has the same.
York