It's necessary to set the clock phase and polarity for DSPI flash or it could not work properly.
Signed-off-by: Gong Qianyu Qianyu.Gong@nxp.com --- arch/arm/dts/fsl-ls1043a-qds.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi index 66efe67..2e9f1f9 100644 --- a/arch/arm/dts/fsl-ls1043a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -28,8 +28,10 @@ #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; - reg = <0>; spi-max-frequency = <1000000>; /* input clock */ + spi-cpol; + spi-cpha; + reg = <0>; };
dflash1: sst25wf040b { @@ -37,6 +39,8 @@ #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3500000>; + spi-cpol; + spi-cpha; reg = <1>; };
@@ -45,6 +49,8 @@ #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3500000>; + spi-cpol; + spi-cpha; reg = <2>; }; };