From: Jimmy Zhang jimmzhang@nvidia.com
Set Seaboard and Harmony to optimal memory settings based on the SOC in use (T20 or T25).
Signed-off-by: Simon Glass sjg@chromium.org --- board/nvidia/common/Makefile | 1 + board/nvidia/common/board.c | 4 + board/nvidia/common/emc.c | 295 ++++++++++++++++++++++++++++++++++++++++++ board/nvidia/common/emc.h | 29 ++++ 4 files changed, 329 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/common/emc.c create mode 100644 board/nvidia/common/emc.h
diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile index 3e748fd..a93d458 100644 --- a/board/nvidia/common/Makefile +++ b/board/nvidia/common/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)lib$(VENDOR).o
COBJS-y += board.o COBJS-$(CONFIG_SPI_UART_SWITCH) += uart-spi-switch.o +COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index cda2417..2569ae1 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -30,6 +30,7 @@ #include <asm/arch/board.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> +#include <asm/arch/emc.h> #include <asm/arch/fuse.h> #include <asm/arch/pinmux.h> #include <asm/arch/pmc.h> @@ -40,6 +41,7 @@ #include <asm/arch/usb.h> #include <i2c.h> #include "board.h" +#include "emc.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -111,6 +113,8 @@ int board_init(void)
#ifdef CONFIG_TEGRA_PMU pmu_set_nominal(); + + board_emc_init(); #endif #endif
diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c new file mode 100644 index 0000000..8be2fba --- /dev/null +++ b/board/nvidia/common/emc.c @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ap20.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/emc.h> +#include <asm/arch/pmu.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/tegra2.h> + +static const struct tegra_emc_table seaboard_emc_tables_hynix_333Mhz[] = { + { + .rate = 166500, /* SDRAM frequency */ + .regs = { + 0x0000000a, /* RC */ + 0x00000021, /* RFC */ + 0x00000008, /* RAS */ + 0x00000003, /* RP */ + 0x00000004, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x0000000c, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000001, /* REXT */ + 0x00000004, /* WDV */ + 0x00000005, /* QUSE */ + 0x00000004, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000d, /* RDV */ + 0x000004df, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000003, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x000000c8, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000006, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x0000000f, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000000, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000083, /* FBIO_CFG5 */ + 0xa04004ae, /* CFG_DIG_DLL */ + 0x007fd010, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000000, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, { + .rate = 333000, /* SDRAM frequency */ + .regs = { + 0x00000014, /* RC */ + 0x00000041, /* RFC */ + 0x0000000f, /* RAS */ + 0x00000005, /* RP */ + 0x00000004, /* R2W */ + 0x00000005, /* W2R */ + 0x00000003, /* R2P */ + 0x0000000c, /* W2P */ + 0x00000005, /* RD_RCD */ + 0x00000005, /* WR_RCD */ + 0x00000003, /* RRD */ + 0x00000001, /* REXT */ + 0x00000004, /* WDV */ + 0x00000005, /* QUSE */ + 0x00000004, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000d, /* RDV */ + 0x000009ff, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000005, /* PCHG2PDEN */ + 0x00000005, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000f, /* RW2PDEN */ + 0x000000c8, /* TXSR */ + 0x00000003, /* TCKE */ + 0x0000000c, /* TFAW */ + 0x00000006, /* TRPAB */ + 0x0000000f, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000000, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000083, /* FBIO_CFG5 */ + 0xe034048b, /* CFG_DIG_DLL */ + 0x007e8010, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000000, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + } +}; + +static const struct tegra_emc_table seaboard_emc_tables_hynix_380Mhz[] = { + { + .rate = 190000, /* SDRAM frequency */ + .regs = { + 0x0000000c, /* RC */ + 0x00000026, /* RFC */ + 0x00000009, /* RAS */ + 0x00000003, /* RP */ + 0x00000004, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x0000000c, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000001, /* REXT */ + 0x00000004, /* WDV */ + 0x00000005, /* QUSE */ + 0x00000004, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000d, /* RDV */ + 0x0000059f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000003, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000b, /* RW2PDEN */ + 0x000000c8, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000007, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x0000000f, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000000, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000083, /* FBIO_CFG5 */ + 0xa06204ae, /* CFG_DIG_DLL */ + 0x007dc010, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000000, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, { + .rate = 380000, /* SDRAM frequency */ + .regs = { + 0x00000017, /* RC */ + 0x0000004b, /* RFC */ + 0x00000012, /* RAS */ + 0x00000006, /* RP */ + 0x00000004, /* R2W */ + 0x00000005, /* W2R */ + 0x00000003, /* R2P */ + 0x0000000c, /* W2P */ + 0x00000006, /* RD_RCD */ + 0x00000006, /* WR_RCD */ + 0x00000003, /* RRD */ + 0x00000001, /* REXT */ + 0x00000004, /* WDV */ + 0x00000005, /* QUSE */ + 0x00000004, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000d, /* RDV */ + 0x00000b5f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000006, /* PCHG2PDEN */ + 0x00000006, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x00000011, /* RW2PDEN */ + 0x000000c8, /* TXSR */ + 0x00000003, /* TCKE */ + 0x0000000e, /* TFAW */ + 0x00000007, /* TRPAB */ + 0x0000000f, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000000, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000083, /* FBIO_CFG5 */ + 0xe044048b, /* CFG_DIG_DLL */ + 0x007d8010, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000000, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + } +}; + +void seaboard_emc_init(void) +{ + switch (tegra_get_chip_type()) { + case TEGRA_SOC_T20: + tegra_set_emc(seaboard_emc_tables_hynix_333Mhz, + ARRAY_SIZE(seaboard_emc_tables_hynix_333Mhz)); + break; + case TEGRA_SOC_T25: + tegra_set_emc(seaboard_emc_tables_hynix_380Mhz, + ARRAY_SIZE(seaboard_emc_tables_hynix_380Mhz)); + break; + default: + /* unknown chip type, no clk change*/ + tegra_set_emc(NULL, 0); + break; + } +} + +struct emc_init { + unsigned int id; /* board id */ + void (*init)(void); +}; + +static struct emc_init board_table[] = { + { + .id = MACH_TYPE_HARMONY, + .init = NULL, + }, + { + .id = MACH_TYPE_SEABOARD, + .init = seaboard_emc_init, + }, +}; + +int board_emc_init(void) +{ + int i; + DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_TEGRA_PMU + /* if voltage has not been set properly, return */ + if (!pmu_is_voltage_nominal()) + return -1; +#endif + for (i = 0; i < ARRAY_SIZE(board_table); i++) { + if (board_table[i].id == gd->bd->bi_arch_number) { + if (board_table[i].init) { + board_table[i].init(); + return 0; + } else + return -1; + } + } + return -1; +} diff --git a/board/nvidia/common/emc.h b/board/nvidia/common/emc.h new file mode 100644 index 0000000..ec1b115 --- /dev/null +++ b/board/nvidia/common/emc.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _NVIDIA_EMC_H_ +#define _NVIDIA_EMC_H_ + +int board_emc_init(void); + +#endif