On Sun, 31 Jan 2021 21:25:39 +0100 Jernej Skrabec jernej.skrabec@siol.net wrote:
Hi Jernej,
It turns out that there is a magic bit in PRCM region which seemingly makes PLLs work if it's enabled. Sadly, there is no documentation what it does exactly, so we'll just mimick BSP boot0 behaviour and enable it before any clock is set up.
Good job of figuring this out!
Fixes: b18bd53d6cde ("sunxi: introduce support for H616 clocks") Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net
arch/arm/mach-sunxi/clock_sun50i_h6.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 06d84eb158d7..68c8e7f2afbe 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -9,6 +9,12 @@ void clock_init_safe(void) { struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#ifdef CONFIG_MACH_SUN50I_H616
Can you change this to: if (IS_ENABLED())?
- /* this seems to enable PLLs */
Out of curiosity, what makes you think it's PLL related? At least the PERIPH0 and CPU PLLs seem to work without it?
Cheers, Andre
- setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10);
+#endif
clock_set_pll1(408000000);
writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);