This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/mach-kirkwood/Kconfig | 1 - board/buffalo/lsxl/Kconfig | 12 -- board/buffalo/lsxl/MAINTAINERS | 7 - board/buffalo/lsxl/Makefile | 6 - board/buffalo/lsxl/README | 139 ------------- board/buffalo/lsxl/kwbimage-lschl.cfg | 211 ------------------- board/buffalo/lsxl/kwbimage-lsxhl.cfg | 211 ------------------- board/buffalo/lsxl/lsxl.c | 279 -------------------------- board/buffalo/lsxl/lsxl.h | 58 ------ configs/lschlv2_defconfig | 42 ---- configs/lsxhl_defconfig | 42 ---- include/configs/lsxl.h | 149 -------------- 12 files changed, 1157 deletions(-) delete mode 100644 board/buffalo/lsxl/Kconfig delete mode 100644 board/buffalo/lsxl/MAINTAINERS delete mode 100644 board/buffalo/lsxl/Makefile delete mode 100644 board/buffalo/lsxl/README delete mode 100644 board/buffalo/lsxl/kwbimage-lschl.cfg delete mode 100644 board/buffalo/lsxl/kwbimage-lsxhl.cfg delete mode 100644 board/buffalo/lsxl/lsxl.c delete mode 100644 board/buffalo/lsxl/lsxl.h delete mode 100644 configs/lschlv2_defconfig delete mode 100644 configs/lsxhl_defconfig delete mode 100644 include/configs/lsxl.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 299977c87d6..9261b606bb4 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -71,7 +71,6 @@ config SYS_SOC default "kirkwood"
source "board/Marvell/openrd/Kconfig" -source "board/buffalo/lsxl/Kconfig" source "board/cloudengines/pogo_e02/Kconfig" source "board/d-link/dns325/Kconfig" source "board/iomega/iconnect/Kconfig" diff --git a/board/buffalo/lsxl/Kconfig b/board/buffalo/lsxl/Kconfig deleted file mode 100644 index ef788963780..00000000000 --- a/board/buffalo/lsxl/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_LSXL - -config SYS_BOARD - default "lsxl" - -config SYS_VENDOR - default "buffalo" - -config SYS_CONFIG_NAME - default "lsxl" - -endif diff --git a/board/buffalo/lsxl/MAINTAINERS b/board/buffalo/lsxl/MAINTAINERS deleted file mode 100644 index facc2dd7d94..00000000000 --- a/board/buffalo/lsxl/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -LSXL BOARD -M: Michael Walle michael@walle.cc -S: Maintained -F: board/buffalo/lsxl/ -F: include/configs/lsxl.h -F: configs/lschlv2_defconfig -F: configs/lsxhl_defconfig diff --git a/board/buffalo/lsxl/Makefile b/board/buffalo/lsxl/Makefile deleted file mode 100644 index 60babb0ded4..00000000000 --- a/board/buffalo/lsxl/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2012 Michael Walle -# Michael Walle michael@walle.cc - -obj-y := lsxl.o diff --git a/board/buffalo/lsxl/README b/board/buffalo/lsxl/README deleted file mode 100644 index ef5ed428806..00000000000 --- a/board/buffalo/lsxl/README +++ /dev/null @@ -1,139 +0,0 @@ -Intro ------ -The Buffalo Linkstation Pro/Live, codename LS-XHL and LS-CHLv2, is a single -disk NAS server. The PCBs of the LS-XHL and LS-CHLv2 are almost the same. -The LS-XHL has a faster CPU and more RAM with a wider data bus, therefore -the LS-XHL PCB has two SDRAM chips. Both have a Kirkwood CPU (Marvell -88F6281). The only on-board storage is a 4 Mbit SPI flash which stores the -bootloader and its environment. The linux kernel and the initial ramdisk -are loaded from the hard disk. - - -Rescue Mode ------------ -These linkstations don't have a populated serial port. There is no way to -access an (unmodified) board other than using the netconsole. If you want -to recover from a bad environment setting or an empty environment, you can -do this only with a working network connection. - -Therefore, on entering the resuce mode, a random ethernet address is -generated if no valid address could be loaded from the environment variable -'ethaddr' and a DHCP request is sent. After a successful DHCP response is -received, the network settings are configured and the ncip is unset. Thus -all netconsole packets are broadcasted and you can use the netconsole to -access board from any host within the network segment. To determine the IP -address assigned to the board, you either have to sniff the traffic or -check the logs/leases of your DHCP server. - -The resuce mode is selected by holding the push button for at least one -second, while powering-on the device. The status LED turns solid amber if -the resuce mode is enabled, thus providing a visual feedback. - -Pressing the same button for at least 10 seconds on power-up will erase the -environment and reset the board. In this case the visual indication will -be: -- blinking blue, for about one second -- solid amber, for about nine seconds -- blinking amber, until you release the button - -This ensures, that you still can recover a device with a broken -environment by first erasing the environment and then entering the rescue -mode. - -Once the rescue mode is started, use the ncb binary from the tools/ -directory to access your board. There is a helper script named -'restore_env' to save your changes. It unsets all the network variables -which were set by the rescue mode, saves your changes and then resets the -board. - -The common use case for this is setting a MAC address. Let us assume you -have an empty environment, the board comes up with the amber LED blinking. -Then you enter the rescue mode, connect to the board with the ncb tool and -use the following commands to set your MAC address: - - setenv ethaddr 00:00:00:00:00:00 - run restore_env - -Of course you need to replace the 00:00:00:00:00:00 with your valid MAC -address, which can be found on a sticker on the bottom of your box. - - -Status LED ----------- -blinking blue - Bootloader is running normally. - -blinking amber - No ethaddr set. Use the `Rescue Mode` to set one. - -blinking red - Something bad happend during loading the operating system. - -The default behavior of the linux kernel is to turn on the blue LED. So if -the blinking blue LED changes to solid blue the kernel was loaded -successfully. - - -Power-on Switch ---------------- -The power-on switch is a software switch. If it is not in ON position when -the bootloader starts, the bootloader will disable the HDD and USB power -and stop the fan. Then it loops until the switch is in ON position again, -enables the power and fan again and continue booting. - - -Boot sources ------------- -The environment defines several different boot sources: - -legacy - This is the default boot source. It loads the kernel and ramdisk from the - attached HDD using the original filenames. The load addresses were - modified to support loading larger kernels. But it should behave the same - as the original bootloader. - -hdd - Use this for new-style booting. Loads three files /vmlinuz, /initrd.img - and /dtb from the boot partition. This should work out of the box if you - have debian and the flash-kernel package installed. - -usb - Same as hdd expect, that the files are loaded from an attached USB mass - storage device and the filename for the device tree is kirkwood-lsxhl.dtb - (or kirkwood-lschlv2.dtb). - -net - Same as usb expect, that the file are loaded from the network. - -rescue - Automatically activated if the push button is pressed for at least one - second on power-up. Does a DHCP request and enables the network console. - See `Rescue Mode` for more information. - -You can change the boot source by setting the 'bootsource' variable to the -corresponding value. Please note, that the restore_env script will the the -bootsource back to 'legacy'. - - -Flash map ---------- -00000 - 5ffff u-boot -60000 - 6ffff reserved, may be used to store dtb -70000 - 7ffff u-boot environment - - -Compiling ---------- -make lsxhl_config (or lschlv2_config) -make u-boot.kwb - - -Update your board ------------------ -Just flash the resulting u-boot.kwb to the beginning of the SPI flash. If -you already have a bootloader CLI, you can use the following commands: - - sf probe 0 - bootp ${loadaddr} u-boot.kwb - sf erase 0 +${filelen} - sf write 0 ${fileaddr} ${filesize} diff --git a/board/buffalo/lsxl/kwbimage-lschl.cfg b/board/buffalo/lsxl/kwbimage-lschl.cfg deleted file mode 100644 index 4493307d87e..00000000000 --- a/board/buffalo/lsxl/kwbimage-lschl.cfg +++ /dev/null @@ -1,211 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2012 Michael Walle -# Michael Walle michael@walle.cc -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0/1 interface pad voltage to 1.8V -DATA 0xFFD100E0 0x1B1B1B9B - -# L2 RAM Timing 0 -DATA 0xFFD20134 0xBBBBBBBB -# not further specified in HW manual, timing taken from original vendor port - -# L2 RAM Timing 1 -DATA 0xFFD20138 0x00BBBBBB -# not further specified in HW manual, timing taken from original vendor port - -# DDR Configuration register -DATA 0xFFD01400 0x43000618 -# bit13-0: 0x618, 1560 DDR2 clks refresh rate -# bit23-14: 0 required -# bit24: 1, enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: 0 required -# bit31-30: 0b01 required - -# DDR Controller Control Low -DATA 0xFFD01404 0x39543000 -# bit3-0: 0 required -# bit4: 0, addr/cmd in same cycle -# bit5: 0, clk is driven during self refresh, we don't care for APX -# bit6: 0, use recommended falling edge of clk for addr/cmd -# bit11-7: 0 required -# bit12: 1 required -# bit13: 1 required -# bit14: 0, input buffer always powered up -# bit17-15: 0 required -# bit18: 1, cpu lock transaction enabled -# bit19: 0 required -# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0, no additional STARTBURST delay - -# DDR Timing (Low) -DATA 0xFFD01408 0x3302444F -# bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0]) -# bit7-4: 4, 5 cycle tRCD -# bit11-8: 4, 5 cyle tRP -# bit15-12: 4, 5 cyle tWR -# bit19-16: 2, 3 cyle tWTR -# bit20: 0, 16 cycle tRAS (tRAS[4]) -# bit23-21: 0 required -# bit27-24: 3, 4 cycle tRRD -# bit31-28: 3, 4 cyle tRTP - -# DDR Timing (High) -DATA 0xFFD0140C 0x00000823 -# bit6-0: 0x23, 35 cycle tRFC -# bit8-7: 0, 1 cycle tR2R -# bit10-9: 0, 1 cyle tR2W -# bit12-11: 1, 2 cylce tW2W -# bit31-13: 0 required - -# DDR Address Control -DATA 0xFFD01410 0x00000009 -# bit1-0: 1, Cs0width=x16 -# bit3-2: 2, Cs0size=512Mbit -# bit5-4: 0, Cs1width=nonexistent -# bit7-6: 0, Cs1size=nonexistent -# bit9-8: 0, Cs2width=nonexistent -# bit11-10: 0, Cs2size=nonexistent -# bit13-12: 0, Cs3width=nonexistent -# bit15-14: 0, Cs3size=nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -# DDR Open Pages Control -DATA 0xFFD01414 0x00000000 -# bit0: 0, OPEn=OpenPage enabled -# bit31-1: 0 required - -# DDR Operation -DATA 0xFFD01418 0x00000000 -# bit3-0: 0, Cmd=Normal SDRAM Mode -# bit31-4: 0 required - -# DDR Mode -DATA 0xFFD0141C 0x00000652 -# bit2-0: 2, Burst Length (2 required) -# bit3: 0, Burst Type (0 required) -# bit6-4: 5, CAS Latency (CL) 5 -# bit7: 0, (Test Mode) Normal operation -# bit8: 0, (Reset DLL) Normal operation -# bit11-9: 3, Write recovery for auto-precharge (3 required) -# bit12: 0, Fast Active power down exit time (0 required) -# bit31-13: 0 required - -# DDR Extended Mode -DATA 0xFFD01420 0x00000042 -# bit0: 0, DRAM DLL enabled -# bit1: 1, DRAM drive strength reduced -# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination) -# bit5-3: 0 required -# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination) -# bit9-7: 0 required -# bit10: 0, differential DQS enabled -# bit11: 0 required -# bit12: 0, DRAM output buffer enabled -# bit31-13: 0 required - -# DDR Controller Control High -DATA 0xFFD01424 0x0000F17F -# bit2-0: 0x7 required -# bit3: 1, MBUS Burst Chop disabled -# bit6-4: 0x7 required -# bit7: 0 required (???) -# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9: 0, no half clock cycle addition to dataout -# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals -# bit11: 0, 1/4 clock cycle skew disabled for write mesh -# bit15-12: 0xf required -# bit31-16: 0 required - -# DDR2 ODT Read Timing (default values) -DATA 0xFFD01428 0x00085520 -# bit3-0: 0 required -# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal -# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal -# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal -# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal -# bit31-20: 0 required - -# DDR2 ODT Write Timing (default values) -DATA 0xFFD0147C 0x00008552 -# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal -# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal -# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal -# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal -# bit31-16: 0 required - -# CS[0]n Base address -DATA 0xFFD01500 0x00000000 -# at 0x0 - -# CS[0]n Size -DATA 0xFFD01504 0x03FFFFF1 -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 0x0, CS0 hit selected -# bit23-4: 0xfffff required -# bit31-24: 0x03, Size (i.e. 64MB) - -# CS[1]n Size -DATA 0xFFD0150C 0x00000000 -# window disabled - -# CS[2]n Size -DATA 0xFFD01514 0x00000000 -# window disabled - -# CS[3]n Size -DATA 0xFFD0151C 0x00000000 -# window disabled - -# DDR ODT Control (Low) -DATA 0xFFD01494 0x003C0000 -# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM -# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM -# bit15-8: 0 required -# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3 -# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1 -# bit31-24: 0 required - -# DDR ODT Control (High) -DATA 0xFFD01498 0x00000000 -# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register -# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register -# bit31-4 0 required - -# CPU ODT Control -DATA 0xFFD0149C 0x0000E80F -# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 -# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 -# bit9-8: 0, Internal ODT assertion is controlled by fiels -# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm -# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm -# bit14: 1, M_STARTBURST_IN ODT enabled -# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values -# bit20-16: 0, Pad N channel driving strength for ODT -# bit25-21: 0, Pad P channel driving strength for ODT -# bit31-26: 0 required - -# DDR Initialization Control -DATA 0xFFD01480 0x00000001 -# bit0: 1, enable DDR init upon this register write -# bit31-1: 0, required - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/buffalo/lsxl/kwbimage-lsxhl.cfg b/board/buffalo/lsxl/kwbimage-lsxhl.cfg deleted file mode 100644 index 4335a663c97..00000000000 --- a/board/buffalo/lsxl/kwbimage-lsxhl.cfg +++ /dev/null @@ -1,211 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2012 Michael Walle -# Michael Walle michael@walle.cc -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0/1 interface pad voltage to 1.8V -DATA 0xFFD100E0 0x1B1B9B9B - -# L2 RAM Timing 0 -DATA 0xFFD20134 0xBBBBBBBB -# not further specified in HW manual, timing taken from original vendor port - -# L2 RAM Timing 1 -DATA 0xFFD20138 0x00BBBBBB -# not further specified in HW manual, timing taken from original vendor port - -# DDR Configuration register -DATA 0xFFD01400 0x43000618 -# bit13-0: 0x618, 1560 DDR2 clks refresh rate -# bit23-14: 0 required -# bit24: 1, enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: 0 required -# bit31-30: 0b01 required - -# DDR Controller Control Low -DATA 0xFFD01404 0x39543010 -# bit3-0: 0 required -# bit4: 1, T2 mode, addr/cmd are driven for two cycles -# bit5: 0, clk is driven during self refresh, we don't care for APX -# bit6: 0, use recommended falling edge of clk for addr/cmd -# bit11-7: 0 required -# bit12: 1 required -# bit13: 1 required -# bit14: 0, input buffer always powered up -# bit17-15: 0 required -# bit18: 1, cpu lock transaction enabled -# bit19: 0 required -# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0, no additional STARTBURST delay - -# DDR Timing (Low) -DATA 0xFFD01408 0x22125441 -# bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0]) -# bit7-4: 4, 5 cycle tRCD -# bit11-8: 4, 5 cyle tRP -# bit15-12: 5, 6 cyle tWR -# bit19-16: 2, 3 cyle tWTR -# bit20: 1, 18 cycle tRAS (tRAS[4]) -# bit23-21: 0 required -# bit27-24: 2, 3 cycle tRRD -# bit31-28: 2, 3 cyle tRTP - -# DDR Timing (High) -DATA 0xFFD0140C 0x00000832 -# bit6-0: 0x32, 50 cycle tRFC -# bit8-7: 0, 1 cycle tR2R -# bit10-9: 0, 1 cyle tR2W -# bit12-11: 1, 2 cylce tW2W -# bit31-13: 0 required - -# DDR Address Control -DATA 0xFFD01410 0x0000000C -# bit1-0: 0, Cs0width=x8 -# bit3-2: 3, Cs0size=1Gbit -# bit5-4: 0, Cs1width=nonexistent -# bit7-6: 0, Cs1size=nonexistent -# bit9-8: 0, Cs2width=nonexistent -# bit11-10: 0, Cs2size=nonexistent -# bit13-12: 0, Cs3width=nonexistent -# bit15-14: 0, Cs3size=nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -# DDR Open Pages Control -DATA 0xFFD01414 0x00000000 -# bit0: 0, OPEn=OpenPage enabled -# bit31-1: 0 required - -# DDR Operation -DATA 0xFFD01418 0x00000000 -# bit3-0: 0, Cmd=Normal SDRAM Mode -# bit31-4: 0 required - -# DDR Mode -DATA 0xFFD0141C 0x00000652 -# bit2-0: 2, Burst Length (2 required) -# bit3: 0, Burst Type (0 required) -# bit6-4: 5, CAS Latency (CL) 5 -# bit7: 0, (Test Mode) Normal operation -# bit8: 0, (Reset DLL) Normal operation -# bit11-9: 3, Write recovery for auto-precharge (3 required) -# bit12: 0, Fast Active power down exit time (0 required) -# bit31-13: 0 required - -# DDR Extended Mode -DATA 0xFFD01420 0x00000006 -# bit0: 0, DRAM DLL enabled -# bit1: 1, DRAM drive strength reduced -# bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination) -# bit5-3: 0 required -# bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination) -# bit9-7: 0 required -# bit10: 0, differential DQS enabled -# bit11: 0 required -# bit12: 0, DRAM output buffer enabled -# bit31-13: 0 required - -# DDR Controller Control High -DATA 0xFFD01424 0x0000F17F -# bit2-0: 0x7 required -# bit3: 1, MBUS Burst Chop disabled -# bit6-4: 0x7 required -# bit7: 0 required (???) -# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9: 0, no half clock cycle addition to dataout -# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals -# bit11: 0, 1/4 clock cycle skew disabled for write mesh -# bit15-12: 0xf required -# bit31-16: 0 required - -# DDR2 ODT Read Timing (default values) -DATA 0xFFD01428 0x00085520 -# bit3-0: 0 required -# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal -# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal -# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal -# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal -# bit31-20: 0 required - -# DDR2 ODT Write Timing (default values) -DATA 0xFFD0147C 0x00008552 -# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal -# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal -# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal -# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal -# bit31-16: 0 required - -# CS[0]n Base address -DATA 0xFFD01500 0x00000000 -# at 0x0 - -# CS[0]n Size -DATA 0xFFD01504 0x0FFFFFF1 -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 0x0, CS0 hit selected -# bit23-4: 0xfffff required -# bit31-24: 0x0f, Size (i.e. 256MB) - -# CS[1]n Size -DATA 0xFFD0150C 0x00000000 -# window disabled - -# CS[2]n Size -DATA 0xFFD01514 0x00000000 -# window disabled - -# CS[3]n Size -DATA 0xFFD0151C 0x00000000 -# window disabled - -# DDR ODT Control (Low) -DATA 0xFFD01494 0x00010000 -# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM -# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM -# bit15-8: 0 required -# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0 -# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM -# bit31-24: 0 required - -# DDR ODT Control (High) -DATA 0xFFD01498 0x00000000 -# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register -# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register -# bit31-4 0 required - -# CPU ODT Control -DATA 0xFFD0149C 0x0000E80F -# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 -# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 -# bit9-8: 0, Internal ODT assertion is controlled by fiels -# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm -# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm -# bit14: 1, M_STARTBURST_IN ODT enabled -# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values -# bit20-16: 0, Pad N channel driving strength for ODT -# bit25-21: 0, Pad P channel driving strength for ODT -# bit31-26: 0 required - -# DDR Initialization Control -DATA 0xFFD01480 0x00000001 -# bit0: 1, enable DDR init upon this register write -# bit31-1: 0, required - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c deleted file mode 100644 index bf69a746e4d..00000000000 --- a/board/buffalo/lsxl/lsxl.c +++ /dev/null @@ -1,279 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2012 Michael Walle - * Michael Walle michael@walle.cc - * - * Based on sheevaplug/sheevaplug.c by - * Marvell Semiconductor <www.marvell.com> - */ - -#include <common.h> -#include <environment.h> -#include <net.h> -#include <malloc.h> -#include <netdev.h> -#include <miiphy.h> -#include <spi.h> -#include <spi_flash.h> -#include <asm/arch/soc.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mpp.h> -#include <asm/arch/gpio.h> - -#include "lsxl.h" - -/* - * Rescue mode - * - * Selected by holding the push button for 3 seconds, while powering on - * the device. - * - * These linkstations don't have a (populated) serial port. There is no - * way to access an (unmodified) board other than using the netconsole. If - * you want to recover from a bad environment setting or an empty environment, - * you can do this only with a working network connection. Therefore, a random - * ethernet address is generated if none is set and a DHCP request is sent. - * After a successful DHCP response is received, the network settings are - * configured and the ncip is unset. Therefore, all netconsole packets are - * broadcasted. - * Additionally, the bootsource is set to 'rescue'. - */ - -#ifndef CONFIG_ENV_OVERWRITE -# error "You need to set CONFIG_ENV_OVERWRITE" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - mvebu_config_gpio(LSXL_OE_VAL_LOW, - LSXL_OE_VAL_HIGH, - LSXL_OE_LOW, LSXL_OE_HIGH); - - /* - * Multi-Purpose Pins Functionality configuration - * These strappings are taken from the original vendor uboot port. - */ - static const u32 kwmpp_config[] = { - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP4_UART0_RXD, - MPP5_UART0_TXD, - MPP6_SYSRST_OUTn, - MPP7_GPO, - MPP8_GPIO, - MPP9_GPIO, - MPP10_GPO, /* HDD power */ - MPP11_GPIO, /* USB Vbus enable */ - MPP12_SD_CLK, - MPP13_SD_CMD, - MPP14_SD_D0, - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_GPO, /* fan speed high */ - MPP19_GPO, /* fan speed low */ - MPP20_GE1_0, - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, - MPP28_GPIO, - MPP29_GPIO, - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, - MPP34_GPIO, - MPP35_GPIO, - MPP36_GPIO, /* function LED */ - MPP37_GPIO, /* alarm LED */ - MPP38_GPIO, /* info LED */ - MPP39_GPIO, /* power LED */ - MPP40_GPIO, /* fan alarm */ - MPP41_GPIO, /* funtion button */ - MPP42_GPIO, /* power switch */ - MPP43_GPIO, /* power auto switch */ - MPP44_GPIO, - MPP45_GPIO, - MPP46_GPIO, - MPP47_GPIO, - MPP48_GPIO, /* function red LED */ - MPP49_GPIO, - 0 - }; - - kirkwood_mpp_conf(kwmpp_config, NULL); - - return 0; -} - -#define LED_OFF 0 -#define LED_ALARM_ON 1 -#define LED_ALARM_BLINKING 2 -#define LED_POWER_ON 3 -#define LED_POWER_BLINKING 4 -#define LED_INFO_ON 5 -#define LED_INFO_BLINKING 6 - -static void __set_led(int blink_alarm, int blink_info, int blink_power, - int value_alarm, int value_info, int value_power) -{ - kw_gpio_set_blink(GPIO_ALARM_LED, blink_alarm); - kw_gpio_set_blink(GPIO_INFO_LED, blink_info); - kw_gpio_set_blink(GPIO_POWER_LED, blink_power); - kw_gpio_set_value(GPIO_ALARM_LED, value_alarm); - kw_gpio_set_value(GPIO_INFO_LED, value_info); - kw_gpio_set_value(GPIO_POWER_LED, value_power); -} - -static void set_led(int state) -{ - switch (state) { - case LED_OFF: - __set_led(0, 0, 0, 1, 1, 1); - break; - case LED_ALARM_ON: - __set_led(0, 0, 0, 0, 1, 1); - break; - case LED_ALARM_BLINKING: - __set_led(1, 0, 0, 1, 1, 1); - break; - case LED_INFO_ON: - __set_led(0, 0, 0, 1, 0, 1); - break; - case LED_INFO_BLINKING: - __set_led(0, 1, 0, 1, 1, 1); - break; - case LED_POWER_ON: - __set_led(0, 0, 0, 1, 1, 0); - break; - case LED_POWER_BLINKING: - __set_led(0, 0, 1, 1, 1, 1); - break; - } -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - set_led(LED_POWER_BLINKING); - - return 0; -} - -#ifdef CONFIG_MISC_INIT_R -static void check_power_switch(void) -{ - if (kw_gpio_get_value(GPIO_POWER_SWITCH)) { - /* turn off fan, HDD and USB power */ - kw_gpio_set_value(GPIO_HDD_POWER, 0); - kw_gpio_set_value(GPIO_USB_VBUS, 0); - kw_gpio_set_value(GPIO_FAN_HIGH, 1); - kw_gpio_set_value(GPIO_FAN_LOW, 1); - set_led(LED_OFF); - - /* loop until released */ - while (kw_gpio_get_value(GPIO_POWER_SWITCH)) - ; - - /* turn power on again */ - kw_gpio_set_value(GPIO_HDD_POWER, 1); - kw_gpio_set_value(GPIO_USB_VBUS, 1); - kw_gpio_set_value(GPIO_FAN_HIGH, 0); - kw_gpio_set_value(GPIO_FAN_LOW, 0); - set_led(LED_POWER_BLINKING); - } -} - -void check_enetaddr(void) -{ - uchar enetaddr[6]; - - if (!eth_env_get_enetaddr("ethaddr", enetaddr)) { - /* signal unset/invalid ethaddr to user */ - set_led(LED_INFO_BLINKING); - } -} - -static void erase_environment(void) -{ - struct spi_flash *flash; - - printf("Erasing environment..\n"); - flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!flash) { - printf("Erasing flash failed\n"); - return; - } - - spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE); - spi_flash_free(flash); - do_reset(NULL, 0, 0, NULL); -} - -static void rescue_mode(void) -{ - printf("Entering rescue mode..\n"); - env_set("bootsource", "rescue"); -} - -static void check_push_button(void) -{ - int i = 0; - - while (!kw_gpio_get_value(GPIO_FUNC_BUTTON)) { - udelay(100000); - i++; - - if (i == 10) - set_led(LED_INFO_ON); - - if (i >= 100) { - set_led(LED_INFO_BLINKING); - break; - } - } - - if (i >= 100) - erase_environment(); - else if (i >= 10) - rescue_mode(); -} - -int misc_init_r(void) -{ - check_power_switch(); - check_enetaddr(); - check_push_button(); - - return 0; -} -#endif - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress(int progress) -{ - if (progress > 0) - return; - - /* this is not an error, eg. bootp with autoload=no will trigger this */ - if (progress == -BOOTSTAGE_ID_NET_LOADED) - return; - - set_led(LED_ALARM_BLINKING); -} -#endif diff --git a/board/buffalo/lsxl/lsxl.h b/board/buffalo/lsxl/lsxl.h deleted file mode 100644 index 8ff3f2f3a9b..00000000000 --- a/board/buffalo/lsxl/lsxl.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2012 Michael Walle - * Michael Walle michael@walle.cc - */ - -#ifndef __LSXL_H -#define __LSXL_H - -#define GPIO_HDD_POWER 10 -#define GPIO_USB_VBUS 11 -#define GPIO_FAN_HIGH 18 -#define GPIO_FAN_LOW 19 -#define GPIO_FUNC_LED 36 -#define GPIO_ALARM_LED 37 -#define GPIO_INFO_LED 38 -#define GPIO_POWER_LED 39 -#define GPIO_FAN_LOCK 40 -#define GPIO_FUNC_BUTTON 41 -#define GPIO_POWER_SWITCH 42 -#define GPIO_POWER_AUTO_SWITCH 43 -#define GPIO_FUNC_RED_LED 48 - -#define _BIT(x) (1<<(x)) - -#define LSXL_OE_LOW (~(_BIT(GPIO_HDD_POWER) \ - | _BIT(GPIO_USB_VBUS) \ - | _BIT(GPIO_FAN_HIGH) \ - | _BIT(GPIO_FAN_LOW))) - -#define LSXL_OE_HIGH (~(_BIT(GPIO_FUNC_LED - 32) \ - | _BIT(GPIO_ALARM_LED - 32) \ - | _BIT(GPIO_INFO_LED - 32) \ - | _BIT(GPIO_POWER_LED - 32) \ - | _BIT(GPIO_FUNC_RED_LED - 32))) - -#define LSXL_OE_VAL_LOW (_BIT(GPIO_HDD_POWER) \ - | _BIT(GPIO_USB_VBUS)) - -#define LSXL_OE_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \ - | _BIT(GPIO_ALARM_LED - 32) \ - | _BIT(GPIO_INFO_LED - 32) \ - | _BIT(GPIO_POWER_LED - 32) \ - | _BIT(GPIO_FUNC_RED_LED - 32)) - -#define LSXL_POL_VAL_LOW (_BIT(GPIO_FAN_HIGH) \ - | _BIT(GPIO_FAN_LOW)) - -#define LSXL_POL_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \ - | _BIT(GPIO_ALARM_LED - 32) \ - | _BIT(GPIO_INFO_LED - 32) \ - | _BIT(GPIO_POWER_LED - 32) \ - | _BIT(GPIO_FUNC_BUTTON - 32) \ - | _BIT(GPIO_POWER_SWITCH - 32) \ - | _BIT(GPIO_POWER_AUTO_SWITCH - 32) \ - | _BIT(GPIO_FUNC_RED_LED - 32)) - -#endif /* __LSXL_H */ diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig deleted file mode 100644 index 7466b6108df..00000000000 --- a/configs/lschlv2_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -CONFIG_ARM=y -CONFIG_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_TARGET_LSXL=y -CONFIG_IDENT_STRING=" LS-CHLv2" -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2" -CONFIG_API=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/sda2" -CONFIG_BOOTCOMMAND="run bootcmd_${bootsource}" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_MISC_INIT_R=y -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lschlv2" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_DM=y -CONFIG_MVSATA_IDE=y -# CONFIG_MMC is not set -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig deleted file mode 100644 index f55a69916ef..00000000000 --- a/configs/lsxhl_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -CONFIG_ARM=y -CONFIG_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_TARGET_LSXL=y -CONFIG_IDENT_STRING=" LS-XHL" -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SYS_EXTRA_OPTIONS="LSXHL" -CONFIG_API=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/sda2" -CONFIG_BOOTCOMMAND="run bootcmd_${bootsource}" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_MISC_INIT_R=y -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lsxhl" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_DM=y -CONFIG_MVSATA_IDE=y -# CONFIG_MMC is not set -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h deleted file mode 100644 index 9d4be184131..00000000000 --- a/include/configs/lsxl.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2012 Michael Walle - * Michael Walle michael@walle.cc - */ - -#ifndef _CONFIG_LSXL_H -#define _CONFIG_LSXL_H - -/* - * Version number information - */ -#if defined(CONFIG_LSCHLV2) -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg -#define CONFIG_MACH_TYPE 3006 -#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */ -#elif defined(CONFIG_LSXHL) -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg -#define CONFIG_MACH_TYPE 2663 -/* CONFIG_SYS_TCLK is 200000000 by default */ -#else -#error "unknown board" -#endif - -/* - * General configuration options - */ -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KW88F6281 /* SOC Name */ - -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_KIRKWOOD_GPIO - -/* - * Commands configuration - */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* loading initramfs images without uimage header */ - -/* ST M25P40 */ -#undef CONFIG_ENV_SPI_MAX_HZ -#define CONFIG_ENV_SPI_MAX_HZ 25000000 -#undef CONFIG_SF_DEFAULT_SPEED -#define CONFIG_SF_DEFAULT_SPEED 25000000 - -/* - * Environment variables configurations - */ -#ifdef CONFIG_SPI_FLASH -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 8 -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */ -#endif - -#define CONFIG_ENV_SIZE 0x10000 /* 64k */ -#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_LOADADDR 0x00800000 - -#if defined(CONFIG_LSXHL) -#define CONFIG_FDTFILE "kirkwood-lsxhl.dtb" -#elif defined(CONFIG_LSCHLV2) -#define CONFIG_FDTFILE "kirkwood-lschlv2.dtb" -#else -#error "Unsupported board" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootsource=legacy\0" \ - "hdpart=0:1\0" \ - "kernel_addr=0x00800000\0" \ - "ramdisk_addr=0x01000000\0" \ - "fdt_addr=0x00ff0000\0" \ - "bootcmd_legacy=ide reset " \ - "&& load ide ${hdpart} ${kernel_addr} /uImage.buffalo " \ - "&& load ide ${hdpart} ${ramdisk_addr} /initrd.buffalo "\ - "&& bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "bootcmd_net=bootp ${kernel_addr} vmlinuz " \ - "&& tftpboot ${ramdisk_addr} initrd.img " \ - "&& setenv ramdisk_len ${filesize} " \ - "&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \ - "&& bootz ${kernel_addr} " \ - "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ - "bootcmd_hdd=ide reset " \ - "&& load ide ${hdpart} ${kernel_addr} /vmlinuz " \ - "&& load ide ${hdpart} ${ramdisk_addr} /initrd.img " \ - "&& setenv ramdisk_len ${filesize} " \ - "&& load ide ${hdpart} ${fdt_addr} /dtb " \ - "&& bootz ${kernel_addr} " \ - "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ - "bootcmd_usb=usb start " \ - "&& load usb 0:1 ${kernel_addr} /vmlinuz " \ - "&& load usb 0:1 ${ramdisk_addr} /initrd.img " \ - "&& setenv ramdisk_len ${filesize} " \ - "&& load usb 0:1 ${fdt_addr} " CONFIG_FDTFILE " " \ - "&& bootz ${kernel_addr} " \ - "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ - "bootcmd_rescue=run config_nc_dhcp; run nc\0" \ - "eraseenv=sf probe 0 " \ - "&& sf erase " __stringify(CONFIG_ENV_OFFSET) \ - " +" __stringify(CONFIG_ENV_SIZE) "\0" \ - "config_nc_dhcp=setenv autoload_old ${autoload}; " \ - "setenv autoload no " \ - "&& bootp " \ - "&& setenv ncip " \ - "&& setenv autoload ${autoload_old}; " \ - "setenv autoload_old\0" \ - "standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \ - "setenv ncip; setenv gatewayip; setenv ethact; " \ - "setenv bootfile; setenv dnsip; " \ - "setenv bootsource legacy; run ser\0" \ - "restore_env=run standard_env; saveenv; reset\0" \ - "ser=setenv stdin serial; setenv stdout serial; " \ - "setenv stderr serial\0" \ - "nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {0, 1} /* enable port 1 only */ -#define CONFIG_PHY_BASE_ADR 7 -#undef CONFIG_RESET_PHY_R -#endif /* CONFIG_CMD_NET */ - -#ifdef CONFIG_IDE -#undef CONFIG_SYS_IDE_MAXBUS -#define CONFIG_SYS_IDE_MAXBUS 1 -#undef CONFIG_SYS_IDE_MAXDEVICE -#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_64BIT_LBA -#endif - -#endif /* _CONFIG_LSXL_H */