Hi!
(adding Marek to Cc again)
On 01.03.2016 14:38, Chin Liang See wrote:
On Tue, 2016-03-01 at 08:23 +0100, Stefan Roese wrote:
On 01.03.2016 07:53, Chin Liang See wrote:
On Mon, 2016-02-29 at 23:55 +0100, Marek Vasut wrote:
On 02/24/2016 09:59 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
Hello Heiko,
Which U-Boot version? Which board?
This is U-Boot v2016.03-rc1. I have custom board with socfpga Arria5 onboard.
Where does this leading 0xff come from? There seems a problem with your spi nor flash driver?
Yes, you're right. I have problems with the driver. As I mentioned in previous mail when I read the contents from the flash some data is corrupted.
How to find out if the problem is because U-Boot has no support for my flash (Spansion S25FL512S NOR flash with SPI) or I have not proper configured SPI in U-Boot?
I believe there is a problem with caches , which we still didn't identify. CCing Dinh and Chin, as they were the last ones looking into this problem.
For now, try doing "dcache off" before using the QSPI NOR.
We managed to get it work for socfpga. One of the issue dragged me long is the CONFIG_SPI_FLASH_USE_4K_SECTORS. Need to ensure its not defined in the defconfig. Hope it helps
This is not clear to me. You mean you were able to reproduce and solve this cache (S-bit) related issue by disabling CONFIG_SPI_FLASH_USE_4K_SECTORS? This option is disabled for all SoCFPGA board in mainline.
Could you please explain in more details what exactly you did to solve this issue on SPI NOR?
Nope, I am not replicating the issue. My board is having Micron instead of Spansion flash. In previously, CONFIG_SPI_FLASH_USE_4K_SECTORS is defined in socfpga as most serial NOR flash are supporting 4k sub sector. With that, it would be good to ensure the 4K is undefined.
In this case, wonder any details on the failure? Intermittent?
I think we are talking about different things here. I'm referring to Marek mentioning the cache problem (S-bit related) on current SoCFPGA U-Boot mainline. With caches enabled you can experience problems on QSPI and on USB (reported from Marek - I didn't test USB yet).
So do you have any updated on this cache / S-bit problem? Or can you use QSPI NOR without any issues on current mainline U-Boot with caches enabled on your platforms?
Thanks, Stefan