[U-Boot] [PATCH 2/3] arm: clean cache management

unify arm cache management except for non standard cache as ARM7TDMI

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com --- Comment fix

Best Regards, J. board/armltd/integratorap/split_by_variant.sh | 18 ++++- cpu/arm1136/cpu.c | 46 +++--------- cpu/arm1176/cpu.c | 57 +-------------- cpu/arm720t/cpu.c | 74 +++--------------- cpu/arm920t/cpu.c | 73 +++---------------- cpu/arm925t/cpu.c | 45 +++--------- cpu/arm926ejs/cpu.c | 72 +++--------------- cpu/arm946es/cpu.c | 48 +++--------- cpu/arm_cortexa8/cpu.c | 39 ---------- cpu/arm_intcm/cpu.c | 15 ---- cpu/ixp/cpu.c | 64 +++------------- cpu/lh7a40x/cpu.c | 70 +++--------------- cpu/pxa/cpu.c | 62 ++------------- cpu/sa1100/cpu.c | 58 ++------------ include/configs/B2.h | 1 + include/configs/assabet.h | 2 + include/configs/cerf250.h | 3 + include/configs/cradle.h | 3 + include/configs/csb226.h | 4 + include/configs/delta.h | 3 + include/configs/dnp1110.h | 2 + include/configs/evb4510.h | 1 + include/configs/gcplus.h | 2 + include/configs/innokom.h | 4 + include/configs/lart.h | 2 + include/configs/logodl.h | 4 + include/configs/lubbock.h | 3 + include/configs/pleb2.h | 3 + include/configs/pxa255_idp.h | 3 + include/configs/shannon.h | 2 + include/configs/trizepsiv.h | 3 + include/configs/wepep250.h | 2 + include/configs/xaeniax.h | 3 + include/configs/xm250.h | 3 + include/configs/xsengine.h | 3 + include/configs/zylonite.h | 3 + lib_arm/Makefile | 3 + cpu/arm926ejs/cpu.c => lib_arm/cache-cp15.c | 100 ++++++++++--------------- 38 files changed, 219 insertions(+), 684 deletions(-) copy cpu/arm926ejs/cpu.c => lib_arm/cache-cp15.c (59%)

diff --git a/board/armltd/integratorap/split_by_variant.sh b/board/armltd/integratorap/split_by_variant.sh index 51dc53f..2c9fe2e 100755 --- a/board/armltd/integratorap/split_by_variant.sh +++ b/board/armltd/integratorap/split_by_variant.sh @@ -84,8 +84,8 @@ else esac fi

-if [ "$cpu" = "arm_intcm" ] -then +case "$cpu" in + arm_intcm) echo "/* Core module undefined/not ported */" >> tmp.fil echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil @@ -102,7 +102,19 @@ then echo "initialization reg */" >> tmp.fil echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil echo " /* CM may not have TCRAM */" >> tmp.fil -fi + echo -n " /* May not be processor " >> tmp.fil + echo "without cache support */" >> tmp.fil + echo "#define CONFIG_SYS_NO_ICACHE 1" >> tmp.fil + echo "#define CONFIG_SYS_NO_DCACHE 1" >> tmp.fil + ;; + + arm720t) + echo -n " /* May not be processor " >> tmp.fil + echo "without cache support */" >> tmp.fil + echo "#define CONFIG_SYS_NO_ICACHE 1" >> tmp.fil + echo "#define CONFIG_SYS_NO_DCACHE 1" >> tmp.fil + ;; +esac

mkdir -p ${obj}include mkdir -p ${obj}board/armltd/integratorap diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c index 0abe307..78f6e92 100644 --- a/cpu/arm1136/cpu.c +++ b/cpu/arm1136/cpu.c @@ -39,13 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif

-static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++); -} +static void cache_flush(void);

int cpu_init (void) { @@ -68,8 +62,6 @@ int cleanup_before_linux (void) * we turn off caches etc ... */

- unsigned long i; - disable_interrupts ();

#ifdef CONFIG_LCD @@ -83,15 +75,12 @@ int cleanup_before_linux (void) #endif

/* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(CR_C | CR_I); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ - asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ - return(0); + cache_flush(); + + return 0; }

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -102,25 +91,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return(0); }

-void icache_enable (void) +static void cache_flush(void) { - ulong reg; + unsigned long i = 0;

- reg = get_cr (); /* get control reg. */ - cp_delay (); - set_cr (reg | CR_I); -} - -void icache_disable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg & ~CR_I); -} - -int icache_status (void) -{ - return(get_cr () & CR_I) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ } diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c index ef78bd9..8aefbe3 100644 --- a/cpu/arm1176/cpu.c +++ b/cpu/arm1176/cpu.c @@ -38,15 +38,6 @@

static void cache_flush (void);

-static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++) - __asm__ __volatile__("nop\n"); -} - int cpu_init (void) { return 0; @@ -66,6 +57,7 @@ int cleanup_before_linux (void) /* turn off I/D-cache */ icache_disable(); dcache_disable(); + /* flush I/D-cache */ cache_flush();

return 0; @@ -95,53 +87,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; }

-void icache_enable (void) -{ - ulong reg; - - reg = get_cr (); /* get control reg. */ - cp_delay (); - set_cr (reg | CR_I); -} - -void icache_disable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg & ~CR_I); -} - -int icache_status (void) -{ - return (get_cr () & CR_I) != 0; -} - -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg | CR_C); -} - -void dcache_disable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg & ~CR_C); -} - -int dcache_status (void) -{ - return (get_cr () & CR_C) != 0; -} - /* flush I/D-cache */ static void cache_flush (void) { diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index d178e41..a6f5c4d 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -36,6 +36,10 @@ #include <asm/hardware.h> #include <asm/system.h>

+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) +static void cache_flush(void); +#endif + int cpu_init (void) { /* @@ -59,17 +63,14 @@ int cleanup_before_linux (void) */

#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - unsigned long i; - disable_interrupts ();

/* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable();

/* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + cache_flush(); #ifdef CONFIG_ARM7_REVD /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; @@ -93,64 +94,13 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); }

-/* - * Instruction and Data cache enable and disable functions - * - */ - -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -void icache_enable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg | CR_C); -} - -void icache_disable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg & ~CR_C); -} - -int icache_status (void) -{ - return (get_cr () & CR_C) != 0; -} - -void dcache_enable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg | CR_C); -} - -void dcache_disable (void) +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; + unsigned long i = 0;

- reg = get_cr (); - cp_delay (); - set_cr (reg & ~CR_C); -} - -int dcache_status (void) -{ - return (get_cr () & CR_C) != 0; + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific cache setup for IntegratorAP/CM720T as yet */ diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c index 83ee3f3..08c9339 100644 --- a/cpu/arm920t/cpu.c +++ b/cpu/arm920t/cpu.c @@ -38,13 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif

-static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} +static void cache_flush(void);

int cpu_init (void) { @@ -67,20 +61,15 @@ int cleanup_before_linux (void) * we turn off caches etc ... */

- unsigned long i; - disable_interrupts ();

/* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(CR_C | CR_I); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + cache_flush();

- return (0); + return 0; }

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -88,55 +77,13 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ - return (0); -} - -void icache_enable (void) -{ - ulong reg; - - reg = get_cr (); /* get control reg. */ - cp_delay (); - set_cr (reg | CR_I); -} - -void icache_disable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg & ~CR_I); -} - -int icache_status (void) -{ - return (get_cr () & CR_I) != 0; -} - -#ifdef USE_920T_MMU -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg | CR_C); + return 0; }

-void dcache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; - - reg = get_cr (); - cp_delay (); - reg &= ~CR_C; - set_cr (reg); -} + unsigned long i = 0;

-int dcache_status (void) -{ - return (get_cr () & CR_C) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); } -#endif diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c index 8d1b562..eb6364d 100644 --- a/cpu/arm925t/cpu.c +++ b/cpu/arm925t/cpu.c @@ -38,13 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif

-static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++); -} +static void cache_flush(void);

int cpu_init (void) { @@ -67,19 +61,16 @@ int cleanup_before_linux (void) * we turn off caches etc ... */

- unsigned long i; - disable_interrupts ();

- /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(CR_C | CR_I); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));

+ /* turn off I/D-cache */ + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - return (0); + cache_flush(); + + return 0; }

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -90,25 +81,11 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); }

-void icache_enable (void) -{ - ulong reg; - - reg = get_cr (); /* get control reg. */ - cp_delay (); - set_cr (reg | CR_I); -} - -void icache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; + unsigned long i = 0;

- reg = get_cr (); - cp_delay (); - set_cr (reg & ~CR_I); + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); }

-int icache_status (void) -{ - return (get_cr () & CR_I) != 0; -} diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c index d1748c9..84c169e 100644 --- a/cpu/arm926ejs/cpu.c +++ b/cpu/arm926ejs/cpu.c @@ -38,13 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif

-static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} +static void cache_flush(void);

int cpu_init (void) { @@ -67,20 +61,16 @@ int cleanup_before_linux (void) * we turn off caches etc ... */

- unsigned long i; - disable_interrupts ();

- /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(CR_C | CR_I); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));

+ /* turn off I/D-cache */ + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + cache_flush();

- return (0); + return 0; }

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -91,52 +81,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); }

-/* cache_bit must be either CR_I or CR_C */ -static void cache_enable(uint32_t cache_bit) -{ - uint32_t reg; - - reg = get_cr(); /* get control reg. */ - cp_delay(); - set_cr(reg | cache_bit); -} - -/* cache_bit must be either CR_I or CR_C */ -static void cache_disable(uint32_t cache_bit) -{ - uint32_t reg; - - reg = get_cr(); - cp_delay(); - set_cr(reg & ~cache_bit); -} - -void icache_enable(void) -{ - cache_enable(CR_I); -} - -void icache_disable(void) -{ - cache_disable(CR_I); -} - -int icache_status(void) -{ - return (get_cr() & CR_I) != 0; -} - -void dcache_enable(void) -{ - cache_enable(CR_C); -} - -void dcache_disable(void) +/* flush I/D-cache */ +static void cache_flush (void) { - cache_disable(CR_C); -} + unsigned long i = 0;

-int dcache_status(void) -{ - return (get_cr() & CR_C) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); } diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c index 25684f2..8d0c533 100644 --- a/cpu/arm946es/cpu.c +++ b/cpu/arm946es/cpu.c @@ -38,13 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif

-static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} +static void cache_flush(void);

int cpu_init (void) { @@ -67,8 +61,6 @@ int cleanup_before_linux (void) * we turn off caches etc ... */

- unsigned long i; - disable_interrupts ();

/* ARM926E-S needs the protection unit enabled for the icache to have @@ -76,15 +68,12 @@ int cleanup_before_linux (void) * should turn off the protection unit as well.... */ /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(CR_C | CR_I); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); - asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); - return (0); + cache_flush(); + + return 0; }

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -96,27 +85,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /*NOTREACHED*/ return (0); } -/* ARM926E-S needs the protection unit enabled for this to have any effect - - left for possible later use */ -void icache_enable (void) -{ - ulong reg;

- reg = get_cr (); /* get control reg. */ - cp_delay (); - set_cr (reg | CR_I); -} - -void icache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; + unsigned long i = 0;

- reg = get_cr (); - cp_delay (); - set_cr (reg & ~CR_I); -} - -int icache_status (void) -{ - return (get_cr () & CR_I) != 0; + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); } diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 506dbec..64ee972 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -46,13 +46,6 @@ void l2cache_disable(void);

static void cache_flush(void);

-static void cp_delay(void) -{ - /* Many OMAP regs need at least 2 nops */ - asm("nop"); - asm("nop"); -} - int cpu_init(void) { /* @@ -111,33 +104,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; }

-void icache_enable(void) -{ - ulong reg; - - reg = get_cr(); /* get control reg. */ - cp_delay(); - set_cr(reg | CR_I); -} - -void icache_disable(void) -{ - ulong reg; - - reg = get_cr(); - cp_delay(); - set_cr(reg & ~CR_I); -} - -void dcache_disable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg & ~CR_C); -} - void l2cache_enable() { unsigned long i; @@ -197,11 +163,6 @@ void l2cache_disable() } }

-int icache_status(void) -{ - return (get_cr() & CR_I) != 0; -} - static void cache_flush(void) { asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c index ccf7fd5..ea6747a 100644 --- a/cpu/arm_intcm/cpu.c +++ b/cpu/arm_intcm/cpu.c @@ -76,18 +76,3 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /*NOTREACHED*/ return (0); } - -/* May not be cahed processor on the CM - do nothing */ -void icache_enable (void) -{ -} - -void icache_disable (void) -{ -} - -/* return "disabled" */ -int icache_status (void) -{ - return 0; -} diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c index 265c820..d9cfbab 100644 --- a/cpu/ixp/cpu.c +++ b/cpu/ixp/cpu.c @@ -42,6 +42,8 @@ ulong loops_per_jiffy; DECLARE_GLOBAL_DATA_PTR; #endif

+static void cache_flush(void); + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { @@ -99,19 +101,16 @@ int cleanup_before_linux (void) * just disable everything that can disturb booting linux */

- unsigned long i; - disable_interrupts ();

/* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable();

/* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + cache_flush();

- return (0); + return 0; }

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -126,55 +125,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); }

-/* cache_bit must be either CR_I or CR_C */ -static void cache_enable(uint32_t cache_bit) -{ - uint32_t reg; - - reg = get_cr(); /* get control reg. */ - cp_delay(); - set_cr(reg | cache_bit); -} - -/* cache_bit must be either CR_I or CR_C */ -static void cache_disable(uint32_t cache_bit) -{ - uint32_t reg; - - reg = get_cr(); - cp_delay(); - set_cr(reg & ~cache_bit); -} - -void icache_enable(void) -{ - cache_enable(CR_I); -} - -void icache_disable(void) -{ - cache_disable(CR_I); -} - -int icache_status(void) +/* flush I/D-cache */ +static void cache_flush (void) { - return (get_cr() & CR_I) != 0; -} + unsigned long i = 0;

-/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); }

/* FIXME */ diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c index 2c6799f..e862251 100644 --- a/cpu/lh7a40x/cpu.c +++ b/cpu/lh7a40x/cpu.c @@ -38,13 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif

-static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} +static void cache_flush(void);

int cpu_init (void) { @@ -67,19 +61,16 @@ int cleanup_before_linux (void) * we turn off caches etc ... */

- unsigned long i; - disable_interrupts ();

/* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(CR_C | CR_I); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable();

/* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - return (0); + cache_flush(); + + return 0; }

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -90,52 +81,11 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); }

-void icache_enable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg | CR_I); -}

-void icache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; + unsigned long i = 0;

- reg = get_cr (); - cp_delay (); - set_cr (reg & ~CR_I); -} - -int icache_status (void) -{ - return (get_cr () & CR_I) != 0; -} - -#ifdef USE_920T_MMU -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg | CR_C); -} - -void dcache_disable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - reg &= ~CR_C; - set_cr (reg); -} - -int dcache_status (void) -{ - return (get_cr () & CR_C) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); } -#endif diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c index e27b6b9..ab58d39 100644 --- a/cpu/pxa/cpu.c +++ b/cpu/pxa/cpu.c @@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; #endif

+static void cache_flush(void); + int cpu_init (void) { /* @@ -60,17 +62,14 @@ int cleanup_before_linux (void) * just disable everything that can disturb booting linux */

- unsigned long i; - disable_interrupts ();

/* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable();

/* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + cache_flush();

return (0); } @@ -87,55 +86,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); }

-/* cache_bit must be either CR_I or CR_C */ -static void cache_enable(uint32_t cache_bit) -{ - uint32_t reg; - - reg = get_cr(); /* get control reg. */ - cp_delay(); - set_cr(reg | cache_bit); -} - -/* cache_bit must be either CR_I or CR_C */ -static void cache_disable(uint32_t cache_bit) -{ - uint32_t reg; - - reg = get_cr(); - cp_delay(); - set_cr(reg & ~cache_bit); -} - -void icache_enable(void) -{ - cache_enable(CR_I); -} - -void icache_disable(void) +/* flush I/D-cache */ +static void cache_flush (void) { - cache_disable(CR_I); -} + unsigned long i = 0;

-int icache_status(void) -{ - return (get_cr() & CR_I) != 0; -} - -/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); }

#ifndef CONFIG_CPU_MONAHANS diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c index d0dfa3d..6c897d0 100644 --- a/cpu/sa1100/cpu.c +++ b/cpu/sa1100/cpu.c @@ -38,6 +38,8 @@ DECLARE_GLOBAL_DATA_PTR; #endif

+static void cache_flush(void); + int cpu_init (void) { /* @@ -59,17 +61,14 @@ int cleanup_before_linux (void) * just disable everything that can disturb booting linux */

- unsigned long i; - disable_interrupts ();

/* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable();

/* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + cache_flush();

return (0); } @@ -86,49 +85,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); }

-static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -void icache_enable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg | CR_C); -} - -void icache_disable (void) -{ - ulong reg; - - reg = get_cr (); - cp_delay (); - set_cr (reg & ~CR_C); -} - -int icache_status (void) -{ - return (get_cr () & CR_C) != 0; -} - -/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - return; -} - -void dcache_disable (void) -{ - return; -} + unsigned long i = 0;

-int dcache_status (void) -{ - return 0; /* always off */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } diff --git a/include/configs/B2.h b/include/configs/B2.h index 01b65c5..35fad5c 100644 --- a/include/configs/B2.h +++ b/include/configs/B2.h @@ -38,6 +38,7 @@ #define CONFIG_B2 1 /* on an B2 Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ #undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#define CONFIG_SYS_NO_CP15_CACHE

#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/

diff --git a/include/configs/assabet.h b/include/configs/assabet.h index a6c442b..8c5b84c 100644 --- a/include/configs/assabet.h +++ b/include/configs/assabet.h @@ -37,6 +37,8 @@ #define CONFIG_ASSABET 1 /* on an Intel Assabet Board */

#undef CONFIG_USE_IRQ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE

#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index 751e03c..82d1401 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -41,6 +41,9 @@

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

+/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 850d93b..75c5f9b 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -37,6 +37,9 @@

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

+/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h index d9f85f0..ed18450 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -42,6 +42,10 @@

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* for timer/console/ethernet */ + +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Hardware drivers */ diff --git a/include/configs/delta.h b/include/configs/delta.h index f5508b7..bacbd90 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -39,6 +39,9 @@ #undef CONFIG_SKIP_RELOCATE_UBOOT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

+/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h index 8f615bd..b6cfc67 100644 --- a/include/configs/dnp1110.h +++ b/include/configs/dnp1110.h @@ -42,6 +42,8 @@ #define CONFIG_DNP1110 1 /* on an DNP/1110 Board */

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE

/* * Size of malloc() pool diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h index ffc9408..0f415d9 100644 --- a/include/configs/evb4510.h +++ b/include/configs/evb4510.h @@ -43,6 +43,7 @@ #define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ #define CONFIG_S3C4510B 1 /* it's a S3C4510B chip */ #define CONFIG_EVB4510 1 /* on an EVB4510 Board */ +#define CONFIG_SYS_NO_CP15_CACHE

#define CONFIG_USE_IRQ #define CONFIG_STACKSIZE_IRQ (4*1024) diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h index 77d4578..b2fbca2 100644 --- a/include/configs/gcplus.h +++ b/include/configs/gcplus.h @@ -49,6 +49,8 @@ #define CONFIG_GCPLUS 1 /* on an ADS GCPlus Board */

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE

#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 895998a..69654c7 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -39,6 +39,10 @@

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* for timer/console/ethernet */ + +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Hardware drivers */ diff --git a/include/configs/lart.h b/include/configs/lart.h index e34ec22..5d6d460 100644 --- a/include/configs/lart.h +++ b/include/configs/lart.h @@ -35,6 +35,8 @@ #define CONFIG_LART 1 /* on an LART Board */

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE

/* * Size of malloc() pool diff --git a/include/configs/logodl.h b/include/configs/logodl.h index 9afa800..889a9a3 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -39,6 +39,10 @@

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* for timer/console/ethernet */ + +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Hardware drivers */ diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index a4b430b..2cf9c02 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -46,6 +46,9 @@

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

+/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h index ab9ea4f..ed873fa 100644 --- a/include/configs/pleb2.h +++ b/include/configs/pleb2.h @@ -42,6 +42,9 @@

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

+/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 5e2e7cf..7485f72 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -68,6 +68,9 @@

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

+/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/configs/shannon.h b/include/configs/shannon.h index c8b0b16..13cc5ff 100644 --- a/include/configs/shannon.h +++ b/include/configs/shannon.h @@ -44,6 +44,8 @@ #define CONFIG_SHANNON 1 /* on an SHANNON/TuxScreen Board */

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE

/* * Size of malloc() pool diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index c2744b5..4917318 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -47,6 +47,9 @@

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

+/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + #define RTC

/* diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h index e74303d..197ac0b 100644 --- a/include/configs/wepep250.h +++ b/include/configs/wepep250.h @@ -27,6 +27,8 @@ #define CONFIG_WEPEP250 1 /* config for wepep250 board */ #undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */

+/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE

/* * Select serial console configuration diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 086ca69..1632d29 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -49,6 +49,9 @@

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

+/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * select serial console configuration */ diff --git a/include/configs/xm250.h b/include/configs/xm250.h index 922eb2c..c8bdf31 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -36,6 +36,9 @@ #define CONFIG_XM250 1 /* on a MicroSys XM250 Board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

+/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool; this lives below the uppermost 128 KiB which are * used for the RAM copy of the uboot code diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index cad414c..7e2abbf 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -35,6 +35,9 @@ #define CONFIG_DOS_PARTITION 1 #define BOARD_LATE_INIT 1 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */

diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 064740d..217636a 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -47,6 +47,9 @@ #undef CONFIG_SKIP_RELOCATE_UBOOT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

+/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/lib_arm/Makefile b/lib_arm/Makefile index c8795b2..3ac9d1f 100644 --- a/lib_arm/Makefile +++ b/lib_arm/Makefile @@ -35,6 +35,9 @@ SOBJS-y += _umodsi3.o COBJS-y += board.o COBJS-y += bootm.o COBJS-y += cache.o +ifndef CONFIG_SYS_NO_CP15_CACHE +COBJS-y += cache-cp15.o +endif COBJS-y += div0.o COBJS-y += interrupts.o

diff --git a/cpu/arm926ejs/cpu.c b/lib_arm/cache-cp15.c similarity index 59% copy from cpu/arm926ejs/cpu.c copy to lib_arm/cache-cp15.c index d1748c9..62ed54f 100644 --- a/cpu/arm926ejs/cpu.c +++ b/lib_arm/cache-cp15.c @@ -1,10 +1,6 @@ /* * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -25,70 +21,17 @@ * MA 02111-1307 USA */

-/* - * CPU specific code - */ - #include <common.h> -#include <command.h> -#include <arm926ejs.h> #include <asm/system.h>

-#ifdef CONFIG_USE_IRQ -DECLARE_GLOBAL_DATA_PTR; -#endif - +#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) static void cp_delay (void) { volatile int i;

/* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -int cpu_init (void) -{ - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - return 0; -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - unsigned long i; - - disable_interrupts (); - - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(CR_C | CR_I); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); + for (i = 0; i < 100; i++) + nop(); }

/* cache_bit must be either CR_I or CR_C */ @@ -110,7 +53,24 @@ static void cache_disable(uint32_t cache_bit) cp_delay(); set_cr(reg & ~cache_bit); } +#endif + +#ifdef CONFIG_SYS_NO_ICACHE +void icache_enable (void) +{ + return; +}

+void icache_disable (void) +{ + return; +} + +int icache_status (void) +{ + return 0; /* always off */ +} +#else void icache_enable(void) { cache_enable(CR_I); @@ -125,7 +85,24 @@ int icache_status(void) { return (get_cr() & CR_I) != 0; } +#endif + +#ifdef CONFIG_SYS_NO_DCACHE +void dcache_enable (void) +{ + return; +} + +void dcache_disable (void) +{ + return; +}

+int dcache_status (void) +{ + return 0; /* always off */ +} +#else void dcache_enable(void) { cache_enable(CR_C); @@ -140,3 +117,4 @@ int dcache_status(void) { return (get_cr() & CR_C) != 0; } +#endif