This patch adds SPL support to the maxbcm MV78460 based board. Including the fixed DDR configuratrion needed for the DDR training code. And the the serdes PHY init code.
Signed-off-by: Stefan Roese sr@denx.de ---
Changes in v2: None
arch/arm/Kconfig | 1 + arch/arm/include/asm/arch-armada-xp/cpu.h | 3 ++ board/maxbcm/kwbimage.cfg | 2 +- board/maxbcm/maxbcm.c | 83 ++++++++++++++++++++++++++++++- configs/maxbcm_defconfig | 5 +- include/configs/maxbcm.h | 47 +++++++++++++++++ 6 files changed, 136 insertions(+), 5 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 07c63e5..9f0e70d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -234,6 +234,7 @@ config TARGET_DB_MV784MP_GP config TARGET_MAXBCM bool "Support maxbcm" select CPU_V7 + select SUPPORT_SPL
config TARGET_DEVKIT3250 bool "Support devkit3250" diff --git a/arch/arm/include/asm/arch-armada-xp/cpu.h b/arch/arm/include/asm/arch-armada-xp/cpu.h index 45fb1ff..4f5ff96 100644 --- a/arch/arm/include/asm/arch-armada-xp/cpu.h +++ b/arch/arm/include/asm/arch-armada-xp/cpu.h @@ -96,6 +96,9 @@ struct kwgpio_registers { u32 irq_level; };
+/* Needed for dynamic (board-specific) mbus configuration */ +extern struct mvebu_mbus_state mbus_state; + /* * functions */ diff --git a/board/maxbcm/kwbimage.cfg b/board/maxbcm/kwbimage.cfg index 5a3bc67..cc05792 100644 --- a/board/maxbcm/kwbimage.cfg +++ b/board/maxbcm/kwbimage.cfg @@ -9,4 +9,4 @@ VERSION 1 BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code -BINARY board/maxbcm/binary.0 0000005b 00000068 +BINARY spl/u-boot-spl.bin 0000005b 00000068 diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c index 94c688f..46b16ac 100644 --- a/board/maxbcm/maxbcm.c +++ b/board/maxbcm/maxbcm.c @@ -11,6 +11,9 @@ #include <asm/arch/soc.h> #include <linux/mbus.h>
+#include "../drivers/ddr/mvebu/ddr3_hw_training.h" +#include "../arch/arm/mvebu-common/serdes/high_speed_env_spec.h" + DECLARE_GLOBAL_DATA_PTR;
/* Base addresses for the external device chip selects */ @@ -19,8 +22,84 @@ DECLARE_GLOBAL_DATA_PTR; #define DEV_CS2_BASE 0xe2000000 #define DEV_CS3_BASE 0xe3000000
-/* Needed for dynamic (board-specific) mbus configuration */ -extern struct mvebu_mbus_state mbus_state; +/* DDR3 static configuration */ +MV_DRAM_MC_INIT ddr3_b0_maxbcm[MV_MAX_DDR3_STATIC_SIZE] = { + {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */ + {0x00001404, 0x30000820}, /* Dunit Control Low Register */ + {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */ + {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */ + {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */ + {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */ + {0x00001418, 0x00000e00}, /* DDR SDRAM Operation Register */ + {0x0000141C, 0x00000672}, /* DDR SDRAM Mode Register */ + {0x00001420, 0x00000004}, /* DDR SDRAM Extended Mode Register */ + {0x00001424, 0x0000F3FF}, /* Dunit Control High Register */ + {0x00001428, 0x0011A940}, /* Dunit Control High Register */ + {0x0000142C, 0x014C5134}, /* Dunit Control High Register */ + {0x0000147C, 0x0000D771}, + + {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */ + {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */ + {0x000014A0, 0x00000001}, + {0x000014A8, 0x00000101}, + + /* Recommended Settings from Marvell for 4 x 16 bit devices: */ + {0x000014C0, 0x192424C9}, /* DRAM addr and Ctrl Driving Strenght*/ + {0x000014C4, 0xAAA24C9}, /* DRAM Data and DQS Driving Strenght */ + + /* + * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the + * training sequence + */ + {0x000200e8, 0x3FFF0E01}, + {0x00020184, 0x3FFFFFE0}, /* Close fast path Window to - 2G */ + + {0x0001504, 0x3FFFFFE1}, /* CS0 Size */ + {0x000150C, 0x00000000}, /* CS1 Size */ + {0x0001514, 0x00000000}, /* CS2 Size */ + {0x000151C, 0x00000000}, /* CS3 Size */ + + {0x0020220, 0x00000007}, /* Reserved */ + + {0x00001538, 0x0000000B}, /* Read Data Sample Delays Register */ + {0x0000153C, 0x0000000B}, /* Read Data Ready Delay Register */ + + {0x000015D0, 0x00000670}, /* MR0 */ + {0x000015D4, 0x00000044}, /* MR1 */ + {0x000015D8, 0x00000018}, /* MR2 */ + {0x000015DC, 0x00000000}, /* MR3 */ + {0x000015E0, 0x00000001}, + {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */ + {0x000015EC, 0xF800A225}, /* DDR PHY */ + + {0x0, 0x0} +}; + +MV_DRAM_MODES maxbcm_ddr_modes[MV_DDR3_MODES_NUMBER] = { + {"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm, NULL}, +}; + +extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; + +/* MAXBCM: SERDES 0-4 PCIE, Serdes 7 = SGMII 0, all others = unconnected */ +MV_BIN_SERDES_CFG maxbcm_serdes_cfg[] = { + { MV_PEX_ROOT_COMPLEX, 0x20011111, 0x00000000, + { PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, + PEX_BUS_DISABLED }, + 0x1f, serdes_change_m_phy + } +}; + +MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) +{ + /* Only one mode supported for this board */ + return &maxbcm_ddr_modes[0]; +} + +MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +{ + return &maxbcm_serdes_cfg[0]; +}
int board_early_init_f(void) { diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index 4bcffd8..219586a 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -1,2 +1,3 @@ -CONFIG_ARM=y -CONFIG_TARGET_MAXBCM=y +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MAXBCM=y diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 005e136..5999d60 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -67,4 +67,51 @@ */ #include "mv-common.h"
+/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40004030 +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds" + +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_SYS_MVEBU_DDR +#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ + #endif /* _CONFIG_DB_MV7846MP_GP_H */