On Tue, Sep 10, 2013 at 12:55:07PM +0530, pekon gupta wrote:
With increase in NAND flash densities occurence of bit-flips has increased. Thus stronger ECC schemes are required for detecting and correcting multiple simultaneous bit-flips in same NAND page. But stronger ECC schemes have large ECC syndrome which require more space in OOB/Spare. This patch add support for BCH16_ECC: (a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data. (b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page >= 26 * (page-size / 512)
Signed-off-by: Pekon Gupta pekon@ti.com
arch/arm/include/asm/arch-am33xx/cpu.h | 15 ++++- arch/arm/include/asm/arch-am33xx/omap_gpmc.h | 4 +- drivers/mtd/nand/omap_gpmc.c | 87 +++++++++++++++++++++++----- include/mtd/mtd-abi.h | 3 +- 4 files changed, 90 insertions(+), 19 deletions(-)
This doesn't apply cleanly.
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 10b56e0..1de92e6 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -63,7 +63,16 @@ struct gpmc_cs { };
struct bch_res_0_3 {
- u32 bch_result_x[4];
- u32 bch_result0;
- u32 bch_result1;
- u32 bch_result2;
- u32 bch_result3;
+};
Is this really an improvement?
It would also be nice if headers for things in drivers/mtd/nand weren't in arch.
-Scott