On Mon, Jun 4, 2018 at 7:05 PM, Marek Vasut marex@denx.de wrote:
On 06/04/2018 03:27 PM, Jagan Teki wrote:
On Fri, May 25, 2018 at 1:28 AM, Marek Vasut marex@denx.de wrote:
The clean_bar() function resets the SPI NOR BAR register to 0, but does not set the flash->curr_bar to 0 , therefore those two can get out of sync, which could ultimatelly result in corrupted flash content.
The simplest test case is this:
=> mw 0x10000000 0x1234abcd 0x4000 => sf probe => sf erase 0x1000000 0x10000 => sf write 0x10000000 0x1000000 0x10000
=> sf probe ; sf read 0x12000000 0 0x10000 ; md 0x12000000
That is, erase a sector above the 16 MiB boundary and write it with random pre-configured data. What will actually happen without this patch is the sector will be erased, but the data will be written to BAR 0 offset 0x0 in the flash.
What I'm trying to say is both erase and write ops we have write_bar to switch specific offset of flash based on the bank_sel and the same bank_sel is updated in flash->bank_curr. If there is an immediate read after we still computing bank_sel and do necessary ops. for each operation completion the clean_bar will switch the flash to 0x0 offset by writing bank_sel as 0
What is corrupting here? can you explain?