Dear Simon Glass,
In message CAPnjgZ3wprPDNUbe0fGbsequXJgQ_bwzkDEu6FeuR-8GG1ndQQ@mail.gmail.com you wrote:
Also I do not understand why it would be needed at all. =A0We did not have such a requirement for any system before, so I feel you must be doing something wrong, or at least very exotic.
I put a fully explanation in the previous patch. Let me just add here
Explanations in some other patch are not available when someone reads the commit message ...
that I see a 100ms delay in the reset code to allow serial output to flush, so there is at least in practice a need for this sort of thing.
Note that such a delay is hardware independent. You implement a special solution that works only for a minority of boards.
For most archs the extra code will be removed by the linker.
Ok, granted.
You may also recall a discussion about a platform where the SPI flash and console uart were muxed, and we had to flush the console uart before switching to SPI. I feel that draining the FIFO could/should be a useful function.
You quote an example of highly specific hardware, which I would not hesitate to call a broken design. I do not really fancy adding code to common files for such exceptional situations.
Best regards,
Wolfgang Denk