Good morning Heiko, Thanks for reviewing. See my reply below.
On Thu, Oct 13, 2011 at 7:42 AM, Heiko Schocher hs@denx.de wrote:
Christian Riesch wrote:
This patch adds a function lpsc_syncreset that allows setting a lpsc module into Sync Reset state.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Cc: Heiko Schocher hs@denx.de Cc: Paulraj Sandeep s-paulraj@ti.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net
arch/arm/cpu/arm926ejs/davinci/psc.c | 20 +++++++++++++++----- arch/arm/include/asm/arch-davinci/hardware.h | 1 + 2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c index 486adb0..e02d1f6 100644 --- a/arch/arm/cpu/arm926ejs/davinci/psc.c +++ b/arch/arm/cpu/arm926ejs/davinci/psc.c @@ -46,7 +46,7 @@ */
/* Works on Always On power domain only (no PD argument) */ -void lpsc_on(unsigned int id) +static void lpsc_transition(unsigned int id, unsigned int state) { dv_reg_p mdstat, mdctl, ptstat, ptcmd; #ifdef CONFIG_SOC_DA8XX @@ -83,10 +83,10 @@ void lpsc_on(unsigned int id) while (readl(ptstat) & 0x01) continue;
- if ((readl(mdstat) & 0x3f) == 0x03)
- return; /* Already on and enabled */
- if ((readl(mdstat) & 0x3f) == state)
- return; /* Already in that state */
- writel(readl(mdctl) | 0x03, mdctl);
- writel((readl(mdctl) & ~0x1f) | state, mdctl);
^ Shouldn't this be ~0x3f ?
I checked the documentation: Actually this should be ~0x07 since the NEXT bitfield (next module state) in the MDCTL register occupies only bits 0..2. The additional bits in the STATE bitfield of the MDSTAT register are used to indicate state transitions.
And we should use a define instead 0x3f ...
Ok, I'll do.
Best regards, Christian