Hi Tom,
Here's the introduction of bare x86 support.
The following changes since commit 4d70b34d7f721d8b1d4d628e68c3a44ab7a10dff:
Merge branch 'master' of git://git.denx.de/u-boot-ubi (2014-11-19 23:18:29 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-x86.git
for you to fetch changes up to fe5b9b447c6eea3873833b1f3ba15c9854aa2ef8:
x86: Rename chromebook-x86 to coreboot (2014-11-21 07:34:16 +0100)
---------------------------------------------------------------- Bin Meng (4): x86: Do CPU identification in the early phase x86: Do TSC MSR calibration only for known/supported CPUs x86: Add quick TSC calibration via PIT x86: Save TSC frequency in the global data
Masahiro Yamada (1): x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory
Simon Glass (43): x86: Remove REALMODE_BASE which is no longer used x86: Remove board_init16() call which is not used x86: Invalidate TLB as early as possible x86: Tidy up global descriptor table setup x86: Use the standard dram_init() function x86: Use the standard arch_cpu_init() function x86: Fix up some missing prototypes x86: Save the BIST value on reset x86: Fix a warning with gcc 4.4.4 Move early malloc() to before arch_cpu_init() fdt: Add a function to decode a variable-sized u32 array dm: serial: Move current serial port pointer to global_data dm: gpio: Add a function to read an ID from a list of GPIOs x86: Add ifdtool for working with Intel Flash Descriptor ROM images x86: config: Move common x86 configs to a common file x86: Add processor functions to halt and get stack pointer x86: Remove unnecessary find_fdt(), prepare_fdt() functions x86: Replace fill_processor_name() with cpu_get_name() x86: Allow timer calibration to work on ivybridge x86: ifdtool: Allow creation of an empty ROM x86: Add chromebook_link board x86: Build a .rom file which can be flashed to an x86 machine x86: Emit post codes in startup code for Chromebooks x86: chromebook_link: Implement CAR support (cache as RAM) x86: Refactor PCI to permit alternate init x86: Support use of PCI before relocation x86: ivybridge: Enable PCI in early init x86: pci: Allow configuration before relocation x86: ivybridge: Add early LPC init so that serial works x86: Tidy up coreboot header usage x86: Add clr/setbits functions x86: Add msr read/write functions that use a structure x86: ivybridge: Perform initial CPU setup x86: ivybridge: Check BIST value on boot x86: ivybridge: Perform Intel microcode update on boot x86: dts: Add microcode updates for ivybridge CPU x86: ivybridge: Add early init for PCH devices x86: ivybridge: Add support for early GPIO init x86: chromebook_link: Enable GPIO support x86: Make show_boot_progress() common x86: ivybridge: Add LAPIC support x86: ivybridge: Implement SDRAM init x86: Rename chromebook-x86 to coreboot
Makefile | 36 ++- arch/x86/Kconfig | 74 ++++- arch/x86/config.mk | 1 - arch/x86/cpu/Makefile | 1 + arch/x86/cpu/coreboot/Makefile | 12 +- arch/x86/cpu/coreboot/coreboot.c | 42 +-- arch/x86/cpu/coreboot/ipchecksum.c | 2 +- arch/x86/cpu/coreboot/pci.c | 22 +- arch/x86/cpu/coreboot/sdram.c | 15 +- arch/x86/cpu/coreboot/tables.c | 6 +- arch/x86/cpu/cpu.c | 301 +++++++++++++++--- arch/x86/cpu/interrupts.c | 2 +- arch/x86/cpu/ivybridge/Kconfig | 172 +++++++++++ arch/x86/cpu/ivybridge/Makefile | 16 + arch/x86/cpu/ivybridge/car.S | 178 +++++++++++ arch/x86/cpu/ivybridge/cpu.c | 357 ++++++++++++++++++++++ arch/x86/cpu/ivybridge/early_init.c | 145 +++++++++ arch/x86/cpu/ivybridge/early_me.c | 191 ++++++++++++ arch/x86/cpu/ivybridge/lpc.c | 48 +++ arch/x86/cpu/ivybridge/me_status.c | 195 ++++++++++++ arch/x86/cpu/ivybridge/microcode_intel.c | 151 ++++++++++ arch/x86/cpu/ivybridge/pci.c | 60 ++++ arch/x86/cpu/ivybridge/report_platform.c | 89 ++++++ arch/x86/cpu/ivybridge/sdram.c | 571 +++++++++++++++++++++++++++++++++++ arch/x86/cpu/pci.c | 98 ++++++ arch/x86/cpu/start.S | 40 ++- arch/x86/cpu/start16.S | 18 +- arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/link.dts | 125 ++++++++ arch/x86/dts/m12206a7_00000028.dtsi | 622 ++++++++++++++++++++++++++++++++++++++ arch/x86/dts/m12306a9_00000017.dtsi | 750 +++++++++++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/arch-coreboot/gpio.h | 5 - arch/x86/include/asm/arch-ivybridge/gpio.h | 10 + arch/x86/include/asm/arch-ivybridge/me.h | 356 ++++++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/microcode.h | 20 ++ arch/x86/include/asm/arch-ivybridge/model_206ax.h | 82 +++++ arch/x86/include/asm/arch-ivybridge/pch.h | 356 ++++++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/pei_data.h | 121 ++++++++ arch/x86/include/asm/arch-ivybridge/sandybridge.h | 109 +++++++ arch/x86/include/asm/config.h | 1 + arch/x86/include/asm/cpu.h | 173 ++++++++++- arch/x86/include/asm/global_data.h | 30 ++ arch/x86/include/asm/gpio.h | 142 ++++++++- arch/x86/include/asm/i8254.h | 3 + arch/x86/include/asm/init_helpers.h | 2 - arch/x86/include/asm/io.h | 49 +++ arch/x86/include/asm/lapic.h | 59 ++++ arch/x86/include/asm/lapic_def.h | 101 +++++++ arch/x86/include/asm/msr.h | 19 ++ arch/x86/include/asm/mtrr.h | 121 ++++++++ arch/x86/include/asm/pci.h | 33 ++ arch/x86/include/asm/post.h | 50 +++ arch/x86/include/asm/processor.h | 21 ++ arch/x86/include/asm/u-boot-x86.h | 17 +- arch/x86/lib/Makefile | 1 + arch/x86/lib/init_helpers.c | 27 -- arch/x86/lib/ramtest.c | 79 +++++ arch/x86/lib/tsc_timer.c | 285 +++++++++++++++++- board/{chromebook-x86 => coreboot}/coreboot/Kconfig | 2 +- board/{chromebook-x86 => coreboot}/coreboot/MAINTAINERS | 2 +- board/{chromebook-x86 => coreboot}/coreboot/Makefile | 0 board/{chromebook-x86 => coreboot}/coreboot/coreboot.c | 0 board/{chromebook-x86 => coreboot}/coreboot/coreboot_start.S | 0 board/google/chromebook_link/Kconfig | 31 ++ board/google/chromebook_link/MAINTAINERS | 6 + board/google/chromebook_link/Makefile | 15 + board/google/chromebook_link/link.c | 124 ++++++++ board/google/common/Makefile | 7 + board/google/common/early_init.S | 29 ++ common/board_f.c | 14 +- configs/chromebook_link_defconfig | 10 + doc/device-tree-bindings/misc/intel-lpc.txt | 23 ++ drivers/gpio/gpio-uclass.c | 19 ++ drivers/gpio/intel_ich6_gpio.c | 79 ++++- drivers/serial/serial-uclass.c | 35 ++- include/asm-generic/global_data.h | 1 + include/asm-generic/gpio.h | 11 +- include/configs/chromebook_link.h | 74 +++++ include/configs/coreboot.h | 265 +--------------- include/configs/x86-common.h | 251 +++++++++++++++ include/fdtdec.h | 18 ++ lib/asm-offsets.c | 3 + lib/fdtdec.c | 22 ++ tools/Makefile | 2 + tools/ifdtool.c | 1039 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ tools/ifdtool.h | 88 ++++++ 87 files changed, 8305 insertions(+), 479 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/Kconfig create mode 100644 arch/x86/cpu/ivybridge/Makefile create mode 100644 arch/x86/cpu/ivybridge/car.S create mode 100644 arch/x86/cpu/ivybridge/cpu.c create mode 100644 arch/x86/cpu/ivybridge/early_init.c create mode 100644 arch/x86/cpu/ivybridge/early_me.c create mode 100644 arch/x86/cpu/ivybridge/lpc.c create mode 100644 arch/x86/cpu/ivybridge/me_status.c create mode 100644 arch/x86/cpu/ivybridge/microcode_intel.c create mode 100644 arch/x86/cpu/ivybridge/pci.c create mode 100644 arch/x86/cpu/ivybridge/report_platform.c create mode 100644 arch/x86/cpu/ivybridge/sdram.c create mode 100644 arch/x86/cpu/pci.c create mode 120000 arch/x86/dts/chromebook_link.dts create mode 100644 arch/x86/dts/m12206a7_00000028.dtsi create mode 100644 arch/x86/dts/m12306a9_00000017.dtsi create mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h create mode 100644 arch/x86/include/asm/arch-ivybridge/me.h create mode 100644 arch/x86/include/asm/arch-ivybridge/microcode.h create mode 100644 arch/x86/include/asm/arch-ivybridge/model_206ax.h create mode 100644 arch/x86/include/asm/arch-ivybridge/pch.h create mode 100644 arch/x86/include/asm/arch-ivybridge/pei_data.h create mode 100644 arch/x86/include/asm/arch-ivybridge/sandybridge.h create mode 100644 arch/x86/include/asm/lapic.h create mode 100644 arch/x86/include/asm/lapic_def.h create mode 100644 arch/x86/include/asm/mtrr.h create mode 100644 arch/x86/include/asm/post.h create mode 100644 arch/x86/lib/ramtest.c rename board/{chromebook-x86 => coreboot}/coreboot/Kconfig (86%) rename board/{chromebook-x86 => coreboot}/coreboot/MAINTAINERS (78%) rename board/{chromebook-x86 => coreboot}/coreboot/Makefile (100%) rename board/{chromebook-x86 => coreboot}/coreboot/coreboot.c (100%) rename board/{chromebook-x86 => coreboot}/coreboot/coreboot_start.S (100%) create mode 100644 board/google/chromebook_link/Kconfig create mode 100644 board/google/chromebook_link/MAINTAINERS create mode 100644 board/google/chromebook_link/Makefile create mode 100644 board/google/chromebook_link/link.c create mode 100644 board/google/common/Makefile create mode 100644 board/google/common/early_init.S create mode 100644 configs/chromebook_link_defconfig create mode 100644 doc/device-tree-bindings/misc/intel-lpc.txt create mode 100644 include/configs/chromebook_link.h create mode 100644 include/configs/x86-common.h create mode 100644 tools/ifdtool.c create mode 100644 tools/ifdtool.h
Regards, Simon