Hi,
On 29-05-15 05:08, Chen-Yu Tsai wrote:
On Thu, May 28, 2015 at 11:22 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Thu, May 28, 2015 at 09:25:31PM +0800, Chen-Yu Tsai wrote:
This adds PSCI support for sun6i. So far it only supports the PWR_ON method.
Signed-off-by: Chen-Yu Tsai wens@csie.org
arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 276 ++++++++++++++++++++++++++++++++++ 2 files changed, 277 insertions(+) create mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 85fbc85..4b783e0 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
ifndef CONFIG_SPL_BUILD ifdef CONFIG_ARMV7_PSCI +obj-$(CONFIG_MACH_SUN6I) += psci_sun6i.o obj-$(CONFIG_MACH_SUN7I) += psci_sun7i.o endif endif diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S new file mode 100644 index 0000000..2516804 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S @@ -0,0 +1,276 @@ +/*
- Copyright (C) 2015 - Chen-Yu Tsai
- Author: Chen-Yu Tsai wens@csie.org
- Based on psci_sun7i.S by Marc Zyngier marc.zyngier@arm.com
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License version 2 as
- published by the Free Software Foundation.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program. If not, see http://www.gnu.org/licenses/.
- */
+#include <config.h> +#include <asm/gic.h> +#include <asm/macro.h> +#include <asm/psci.h> +#include <asm/arch/cpu.h>
+/*
- Memory layout:
- SECURE_RAM to text_end :
- ._secure_text section
- text_end to ALIGN_PAGE(text_end):
- nothing
- ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
- 1kB of stack per CPU (4 CPUs max).
- */
.pushsection ._secure.text, "ax".arch_extension sec+#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000) +#define TEN_MS (10 * ONE_MS) +#define GICD_BASE 0x1c81000 +#define GICC_BASE 0x1c82000
+.macro timer_wait reg, ticks
@ Program CNTP_TVALmovw \reg, #(\ticks & 0xffff)movt \reg, #(\ticks >> 16)mcr p15, 0, \reg, c14, c2, 0isb@ Enable physical timer, mask interruptmov \reg, #3mcr p15, 0, \reg, c14, c2, 1@ Poll physical timer until ISTATUS is on+1: isb
mrc p15, 0, \reg, c14, c2, 1ands \reg, \reg, #4bne 1b@ Disable timermov \reg, #0mcr p15, 0, \reg, c14, c2, 1isb+.endm
I think I saw some patch to factorize that out. In the Tegra K1 PSCI patches iirc.
Waiting for v2: https://patchwork.ozlabs.org/patch/471694/
Note I plan to merge this patch-set as is. I agree that factoring out this bit into a helper is a good idea, but that can be done as a later cleanup.
Regards,
Hans