On 12/05/21 11:50 am, Vignesh Raghavendra wrote:
On 5/12/21 11:40 AM, Lokesh Vutla wrote:
On 11/05/21 11:34 am, Vignesh Raghavendra wrote:
On 5/11/21 10:21 AM, Lokesh Vutla wrote:
On 10/05/21 10:54 pm, Vignesh Raghavendra wrote:
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING CFG, TCHAN CFG and RCHAN CFG address ranges.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++++++++++ .../k3-j7200-common-proc-board-u-boot.dtsi | 26 +++++++++++++++++++ .../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++++++++
If these are specific to R5, then it should be moved to R5 dts no? -u-boot.dtsi will be applied to A53 dts as well.
Not really.. There registers are present within respective IPs. A53/A72 use DM APIs to configure these registers whereas R5 does direct programming. I intend to add these ranges to kernel DT as well. Until then, will be in -u-boot.dtsi.
You intend to add mcu-navss ringacc to kernel dts as well. I am fine with this.
MCU RINGACC node itself is present in kernel dts, its just cfg register ranges that are not populated.
okay, please mention this intention in commit description. It says needed only for R5 but code is in u-boot.dtsi with the intention of being added in kernel dts. It is confusing.
Thanks and regards, Lokesh