The clock access functions exported by the clk header use the struct clk_ti_reg parameter to get the address of the register. This must also apply to clk_ti_latch(). Changes to TI's clk-mux and clk-divider drivers prevented the patch from generating compile errors.
Signed-off-by: Dario Binacchi dariobin@libero.it ---
(no changes since v1)
drivers/clk/ti/clk-divider.c | 20 ++++++++++++-------- drivers/clk/ti/clk-mux.c | 20 ++++++++++---------- drivers/clk/ti/clk.c | 10 +++++----- drivers/clk/ti/clk.h | 2 +- 4 files changed, 28 insertions(+), 24 deletions(-)
diff --git a/drivers/clk/ti/clk-divider.c b/drivers/clk/ti/clk-divider.c index 270f2fbdf0..15941f1781 100644 --- a/drivers/clk/ti/clk-divider.c +++ b/drivers/clk/ti/clk-divider.c @@ -27,7 +27,7 @@
struct clk_ti_divider_priv { struct clk parent; - fdt_addr_t reg; + struct clk_ti_reg reg; const struct clk_div_table *table; u8 shift; u8 flags; @@ -200,11 +200,11 @@ static ulong clk_ti_divider_set_rate(struct clk *clk, ulong rate)
val = _get_val(priv->table, priv->div_flags, div);
- v = readl(priv->reg); + v = clk_ti_readl(&priv->reg); v &= ~(priv->mask << priv->shift); v |= val << priv->shift; - writel(v, priv->reg); - clk_ti_latch(priv->reg, priv->latch); + clk_ti_writel(v, &priv->reg); + clk_ti_latch(&priv->reg, priv->latch);
return clk_get_rate(clk); } @@ -220,7 +220,7 @@ static ulong clk_ti_divider_get_rate(struct clk *clk) if (IS_ERR_VALUE(parent_rate)) return parent_rate;
- v = readl(priv->reg) >> priv->shift; + v = clk_ti_readl(&priv->reg) >> priv->shift; v &= priv->mask;
div = _get_div(priv->table, priv->div_flags, v); @@ -287,10 +287,14 @@ static int clk_ti_divider_of_to_plat(struct udevice *dev) u32 min_div = 0; u32 max_val, max_div = 0; u16 mask; - int i, div_num; + int i, div_num, err; + + err = clk_ti_get_reg_addr(dev, 0, &priv->reg); + if (err) { + dev_err(dev, "failed to get register address\n"); + return err; + }
- priv->reg = dev_read_addr(dev); - dev_dbg(dev, "reg=0x%08lx\n", priv->reg); priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0); priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL); if (dev_read_bool(dev, "ti,index-starts-at-one")) diff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c index bb5e49e114..215241b161 100644 --- a/drivers/clk/ti/clk-mux.c +++ b/drivers/clk/ti/clk-mux.c @@ -17,7 +17,7 @@
struct clk_ti_mux_priv { struct clk_bulk parents; - fdt_addr_t reg; + struct clk_ti_reg reg; u32 flags; u32 mux_flags; u32 mask; @@ -58,7 +58,7 @@ static int clk_ti_mux_get_index(struct clk *clk) struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev); u32 val;
- val = readl(priv->reg); + val = clk_ti_readl(&priv->reg); val >>= priv->shift; val &= priv->mask;
@@ -91,13 +91,13 @@ static int clk_ti_mux_set_parent(struct clk *clk, struct clk *parent) if (priv->flags & CLK_MUX_HIWORD_MASK) { val = priv->mask << (priv->shift + 16); } else { - val = readl(priv->reg); + val = clk_ti_readl(&priv->reg); val &= ~(priv->mask << priv->shift); }
val |= index << priv->shift; - writel(val, priv->reg); - clk_ti_latch(priv->reg, priv->latch); + clk_ti_writel(val, &priv->reg); + clk_ti_latch(&priv->reg, priv->latch); return 0; }
@@ -215,14 +215,14 @@ static int clk_ti_mux_probe(struct udevice *dev) static int clk_ti_mux_of_to_plat(struct udevice *dev) { struct clk_ti_mux_priv *priv = dev_get_priv(dev); + int err;
- priv->reg = dev_read_addr(dev); - if (priv->reg == FDT_ADDR_T_NONE) { - dev_err(dev, "failed to get register\n"); - return -EINVAL; + err = clk_ti_get_reg_addr(dev, 0, &priv->reg); + if (err) { + dev_err(dev, "failed to get register address\n"); + return err; }
- dev_dbg(dev, "reg=0x%08lx\n", priv->reg); priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0); priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 7a413d668d..6e5cc90f0f 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -23,17 +23,17 @@ struct clk_iomap { static unsigned int clk_memmaps_num; static struct clk_iomap clk_memmaps[CLK_MAX_MEMMAPS];
-static void clk_ti_rmw(u32 val, u32 mask, fdt_addr_t reg) +static void clk_ti_rmw(u32 val, u32 mask, struct clk_ti_reg *reg) { u32 v;
- v = readl(reg); + v = clk_ti_readl(reg); v &= ~mask; v |= val; - writel(v, reg); + clk_ti_writel(v, reg); }
-void clk_ti_latch(fdt_addr_t reg, s8 shift) +void clk_ti_latch(struct clk_ti_reg *reg, s8 shift) { u32 latch;
@@ -44,7 +44,7 @@ void clk_ti_latch(fdt_addr_t reg, s8 shift)
clk_ti_rmw(latch, latch, reg); clk_ti_rmw(0, latch, reg); - readl(reg); /* OCP barrier */ + clk_ti_readl(reg); /* OCP barrier */ }
void clk_ti_writel(u32 val, struct clk_ti_reg *reg) diff --git a/drivers/clk/ti/clk.h b/drivers/clk/ti/clk.h index ea36d065ac..96859f9dea 100644 --- a/drivers/clk/ti/clk.h +++ b/drivers/clk/ti/clk.h @@ -8,7 +8,6 @@ #ifndef _CLK_TI_H #define _CLK_TI_H
-void clk_ti_latch(fdt_addr_t reg, s8 shift); /** * struct clk_ti_reg - TI register declaration * @offset: offset from the master IP module base address @@ -19,6 +18,7 @@ struct clk_ti_reg { u8 index; };
+void clk_ti_latch(struct clk_ti_reg *reg, s8 shift); void clk_ti_writel(u32 val, struct clk_ti_reg *reg); u32 clk_ti_readl(struct clk_ti_reg *reg); int clk_ti_get_reg_addr(struct udevice *dev, int index, struct clk_ti_reg *reg);