Signed-off-by: Santan Kumar santan.kumar@nxp.com Signed-off-by: Priyanka Jain priyanka.jain@nxp.com Signed-off-by: Abhimanyu Saini abhimanyu.saini@nxp.com --- Changes for v3: Rebased to latest codebase
Depends on York MMU patches: http://patchwork.ozlabs.org/bundle/yorksun/Rewrite_MMU/ For correct type of image creation: https://patchwork.ozlabs.org/patch/671466/
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 +-- .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 6 +-- board/freescale/ls2080a/ls2080a.c | 6 +-- board/freescale/ls2080aqds/eth.c | 8 +--- board/freescale/ls2080aqds/ls2080aqds.c | 4 +- configs/ls2080aqds_sdcard_defconfig | 53 ++++++++++++++++++++++ include/configs/ls2080a_common.h | 9 ++++ include/configs/ls2080aqds.h | 33 ++++++++++++-- 8 files changed, 105 insertions(+), 20 deletions(-) create mode 100644 configs/ls2080aqds_sdcard_defconfig
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 17258a7..d9e2a90 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -435,7 +435,7 @@ int cpu_eth_init(bd_t *bis) { int error = 0;
-#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) error = fsl_mc_ldpaa_init(bis); #endif #ifdef CONFIG_FMAN_ENET @@ -571,7 +571,7 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size) { phys_size_t ram_top = ram_size;
-#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) /* The start address of MC reserved memory needs to be aligned. */ ram_top -= mc_get_dram_block_size(); ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); @@ -686,7 +686,7 @@ void dram_init_banksize(void) } #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
-#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bd->bi_dram[2].size >= diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 7faa86c..10d7f47 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -18,7 +18,7 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; #endif
-#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) int xfi_dpmac[XFI8 + 1]; int sgmii_dpmac[SGMII16 + 1]; #endif @@ -103,7 +103,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, debug("Unknown SerDes lane protocol %d\n", lane_prtcl); else { serdes_prtcl_map[lane_prtcl] = 1; -#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) switch (lane_prtcl) { case QSGMII_A: wriop_init_dpmac(sd, 5, (int)lane_prtcl); @@ -152,7 +152,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
void fsl_serdes_init(void) { -#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) int i , j;
for (i = XFI1, j = 1; i <= XFI8; i++, j++) diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index ace5bf6..cff468b 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -64,13 +64,13 @@ int board_eth_init(bd_t *bis) error = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif
-#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) error = cpu_eth_init(bis); #endif return error; }
-#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) void fdt_fixup_board_enet(void *fdt) { int offset; @@ -128,7 +128,7 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory_banks(blob, base, size, 2);
-#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) fdt_fixup_board_enet(blob); #endif
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 59361e9..302ff76 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -22,7 +22,7 @@
#define MC_BOOT_ENV_VAR "mcinitcmd"
-#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks. * Bank 1 -> Lanes A, B, C, D, E, F, G, H * Bank 2 -> Lanes A,B, C, D, E, F, G, H @@ -834,8 +834,8 @@ void ls2080a_handle_phy_interface_xsgmii(int i) int board_eth_init(bd_t *bis) { int error; +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) char *mc_boot_env_var; -#ifdef CONFIG_FSL_MC_ENET struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) @@ -918,7 +918,3 @@ int board_eth_init(bd_t *bis) error = pci_eth_init(bis); return error; } - -#ifdef CONFIG_FSL_MC_ENET - -#endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 291df4c..2ed8b42 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -264,7 +264,7 @@ int arch_misc_init(void) } #endif
-#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) void fdt_fixup_board_enet(void *fdt) { int offset; @@ -320,7 +320,7 @@ int ft_board_setup(void *blob, bd_t *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
-#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) fdt_fixup_board_enet(blob); #endif
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig new file mode 100644 index 0000000..874d49e --- /dev/null +++ b/configs/ls2080aqds_sdcard_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_DM_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index ae72939..610dfe9 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -200,9 +200,16 @@ unsigned long long get_qixis_addr(void); "earlycon=uart8250,mmio,0x21c0500 " \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=256" +#if defined(CONFIG_SD_BOOT) +#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80200000 0x3800 0x800;"\ + " fsl_mc apply dpl 0x80200000 &&" \ + " mmc read $kernel_load $kernel_start" \ + " $kernel_size && bootm $kernel_load" +#else #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ " cp.b $kernel_start $kernel_load" \ " $kernel_size && bootm $kernel_load" +#endif
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ @@ -230,6 +237,8 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_SPL_MMC_SUPPORT #endif #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 93f6b51..d3eea59 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -116,7 +116,9 @@ unsigned long get_board_ddr_clk(void); CONFIG_SYS_FLASH_BASE + 0x40000000} #endif
+#ifndef CONFIG_FSL_QSPI #define CONFIG_NAND_FSL_IFC +#endif #define CONFIG_SYS_NAND_MAX_ECCPOS 256 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
@@ -151,10 +153,12 @@ unsigned long get_board_ddr_clk(void); FTIM2_NAND_TWHRE(0x1e)) #define CONFIG_SYS_NAND_FTIM3 0x0
+#ifndef CONFIG_FSL_QSPI #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND +#endif
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
@@ -165,12 +169,14 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 #define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_SD 0x00 #define QIXIS_LBMAP_QSPI 0x0f #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RCW_SRC_NAND 0x107 +#define QIXIS_RCW_SRC_SD 0x40 #define QIXIS_RCW_SRC_QSPI 0x62 #define QIXIS_RST_FORCE_MEM 0x01
@@ -234,6 +240,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x200000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x20000 #endif #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT @@ -374,7 +385,23 @@ unsigned long get_board_ddr_clk(void); "esbc_validate 0x580cc0000;" \ "fsl_mc start mc 0x580300000" \ " 0x580800000 \0" -#else +#endif /* CONFIG_SECURE_BOOT */ +#ifdef CONFIG_SD_BOOT +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x800\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x8800\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x14000\0" \ + "mcinitcmd=mmcinfo;mmc read 0x80000000 0x1800 0x800;" \ + "mmc read 0x80100000 0x4000 0x800;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" +#else /* NOR_BOOT */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ @@ -388,10 +415,10 @@ unsigned long get_board_ddr_clk(void); "kernel_size=0x2800000\0" \ "mcinitcmd=fsl_mc start mc 0x580300000" \ " 0x580800000 \0" -#endif /* CONFIG_SECURE_BOOT */ +#endif
-#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) #define CONFIG_FSL_MEMAC #define CONFIG_PHYLIB #define CONFIG_PHYLIB_10G