Yuli Barcohen wrote:
As I mentioned, it's for byte lanes swapping. If you connect a 16-bit flash chip to a PPC, you need to connect only two byte lanes of the PPC data bus i.e. lines D0-D15. For PPC, D0 is MSB and D15 is LSB. For the flash, D0 is LSB and D15 is MSB. So, you can connect D0 to D15, D1 to D14, and so on.
This is the correct way of interfacing flash chip per PowerPC documentation.
Another possibility D0-D7 of PPC to D7-D0 of the flash and D8-D15 of PPC to D15-D8 of the flash. The latter case is the case of swapped byte lanes because PPC's most significant byte goes always to D0-D7 and thus to the least significant byte of the flash.
This is really not the correct way to interface the Flash. It seems like hardware designer goofed up and asking the software guys to fix his/her mess.
So, in the latter case, you have to define CFG_FLASH_CFI_SWAP. Without CFG_FLASH_CFI_SWAP, any flash command (which is always single byte) will go to PPC's D8-D15 and consequently to the most significant byte of the flash. This won't work because the commands must go to the flash's least significant byte. Of course, PPC is only an example, the same problem can occur with other CPUs too, it only depends on the bus architecture.
Really it depends on the designer. The hardware designer can scramble the data bus in many more ways.
Best regards, Tolunay